Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS

Michael Feilen; Andreas Iliopoulos; Michael Vonbun; Walter Stechele

doi:10.1109/FPL.2013.6645521

Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS

Michael Feilen, Andreas Iliopoulos, Michael Vonbun, Walter Stechele

Chair of Integrated Systems

Technical University of Munich

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

Temporal runtime-reconfiguration of FPGAs allows for a resource-efficient sequential execution of signal processing modules. Approaches for partitioning processing chains into modules have been derived in various previous works. We will present a metric for weighted partitioning of pre-defined processing element sequences. The proposed method yields a set of reconfigurable partitions, which are balanced in terms of resources, while jointly have a minimal data throughput. Using this metric, we will formulate a partitioning algorithm with linear complexity and will compare our approach to the state of the art.

Original language	English
DOIs	https://doi.org/10.1109/FPL.2013.6645521
State	Published - 2013
Event	2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Porto, Portugal Duration: 2 Sep 2013 → 4 Sep 2013

Conference

Conference	2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013
Country/Territory	Portugal
City	Porto
Period	2/09/13 → 4/09/13

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10.1109/FPL.2013.6645521

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abstract = "Temporal runtime-reconfiguration of FPGAs allows for a resource-efficient sequential execution of signal processing modules. Approaches for partitioning processing chains into modules have been derived in various previous works. We will present a metric for weighted partitioning of pre-defined processing element sequences. The proposed method yields a set of reconfigurable partitions, which are balanced in terms of resources, while jointly have a minimal data throughput. Using this metric, we will formulate a partitioning algorithm with linear complexity and will compare our approach to the state of the art.",

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doi = "10.1109/FPL.2013.6645521",

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AU - Iliopoulos, Andreas

AU - Vonbun, Michael

AU - Stechele, Walter

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N2 - Temporal runtime-reconfiguration of FPGAs allows for a resource-efficient sequential execution of signal processing modules. Approaches for partitioning processing chains into modules have been derived in various previous works. We will present a metric for weighted partitioning of pre-defined processing element sequences. The proposed method yields a set of reconfigurable partitions, which are balanced in terms of resources, while jointly have a minimal data throughput. Using this metric, we will formulate a partitioning algorithm with linear complexity and will compare our approach to the state of the art.

AB - Temporal runtime-reconfiguration of FPGAs allows for a resource-efficient sequential execution of signal processing modules. Approaches for partitioning processing chains into modules have been derived in various previous works. We will present a metric for weighted partitioning of pre-defined processing element sequences. The proposed method yields a set of reconfigurable partitions, which are balanced in terms of resources, while jointly have a minimal data throughput. Using this metric, we will formulate a partitioning algorithm with linear complexity and will compare our approach to the state of the art.

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U2 - 10.1109/FPL.2013.6645521

DO - 10.1109/FPL.2013.6645521

M3 - Paper

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T2 - 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013

Y2 - 2 September 2013 through 4 September 2013

ER -

Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS

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