V_minTesting under Variations: Defect vs. Fault Coverage

It has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into easily detectable stuck-at-faults. It is often overlooked that Vmin testing poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under Vmin is a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first test pattern generation algorithm specifically tuned for Vmin testing which obtains higher fault coverage by smaller test sets than those generated for nominal voltage. Finally, it is shown that patterns generated for Vmin are also beneficial under nominal voltage with respect to both fault coverage and pattern count.