TY - GEN
T1 - VminTesting under Variations
T2 - 25th IEEE Latin American Test Symposium, LATS 2024
AU - Jafarzadeh, Hanieh
AU - Klemme, Florian
AU - Amrouch, Hussam
AU - Hellebrand, Sybille
AU - Wunderlich, Hans Joachim
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - It has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into easily detectable stuck-at-faults. It is often overlooked that Vmin testing poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under Vmin is a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first test pattern generation algorithm specifically tuned for Vmin testing which obtains higher fault coverage by smaller test sets than those generated for nominal voltage. Finally, it is shown that patterns generated for Vmin are also beneficial under nominal voltage with respect to both fault coverage and pattern count.
AB - It has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into easily detectable stuck-at-faults. It is often overlooked that Vmin testing poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under Vmin is a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first test pattern generation algorithm specifically tuned for Vmin testing which obtains higher fault coverage by smaller test sets than those generated for nominal voltage. Finally, it is shown that patterns generated for Vmin are also beneficial under nominal voltage with respect to both fault coverage and pattern count.
KW - Low Voltage Testing
KW - Small Delay Faults
KW - Vmin Testing under Variations
UR - http://www.scopus.com/inward/record.url?scp=85195426186&partnerID=8YFLogxK
U2 - 10.1109/LATS62223.2024.10534608
DO - 10.1109/LATS62223.2024.10534608
M3 - Conference contribution
AN - SCOPUS:85195426186
T3 - 2024 IEEE 25th Latin American Test Symposium, LATS 2024
BT - 2024 IEEE 25th Latin American Test Symposium, LATS 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 April 2024 through 12 April 2024
ER -