Abstract
This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level description. The idea is, not to synthesize system level implementations of communication and synchronization mechanisms but to perform the synthesis step as a mapping step of an abstract communication or synchronization mechanism to one of a set of RT-level implementations. The major sub-problem, which needed to be solved for the synthesis algorithm was the topology dependent mapping of implementations.
| Original language | English |
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| Pages | 458-462 |
| Number of pages | 5 |
| State | Published - 1995 |
| Externally published | Yes |
| Event | Proceedings of the 1995 European Design Automation Conference with EURO-VHDL - Brighton, UK Duration: 18 Sep 1995 → 22 Sep 1995 |
Conference
| Conference | Proceedings of the 1995 European Design Automation Conference with EURO-VHDL |
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| City | Brighton, UK |
| Period | 18/09/95 → 22/09/95 |