VHDL-based communication- and synchronization synthesis

Wolfgang Ecker, Manfred Huber

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations


This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level description. The idea is, not to synthesize system level implementations of communication and synchronization mechanisms but to perform the synthesis step as a mapping step of an abstract communication or synchronization mechanism to one of a set of RT-level implementations. The major sub-problem, which needed to be solved for the synthesis algorithm was the topology dependent mapping of implementations.

Original languageEnglish
Number of pages5
StatePublished - 1995
Externally publishedYes
EventProceedings of the 1995 European Design Automation Conference with EURO-VHDL - Brighton, UK
Duration: 18 Sep 199522 Sep 1995


ConferenceProceedings of the 1995 European Design Automation Conference with EURO-VHDL
CityBrighton, UK


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