VHDL 200× - requirements from testbench-view

Matthias Bauer; Wolfgang Ecker; Mike Heuchling

VHDL 200× - requirements from testbench-view

Matthias Bauer, Wolfgang Ecker, Mike Heuchling

Siemens AG

Research output: Contribution to conference › Paper › peer-review

Abstract

Both, requirements for VHDL and restrictions to VHDL standards are discussed by many groups and forums. A problem to be solved is to handle the growing complexity of hardware designs and test environments. Aim of the paper is to support the discussion by defining requirements impacted by modern verification techniques. We focus on performance and modeling aspects from testbench development view. Therefore we consider simulation methodologies, coding styles and in particular VHDL extensions. Further, impacts on VHDL extensions by modern requirement engineering methodologies are dealt with.

Original language	English
Pages	39-41
Number of pages	3
State	Published - 1998
Externally published	Yes
Event	Proceedings of the 1998 International Verilog HDL Conference - Santa Clara, CA, USA Duration: 16 Mar 1998 → 19 Mar 1998

Conference

Conference	Proceedings of the 1998 International Verilog HDL Conference
City	Santa Clara, CA, USA
Period	16/03/98 → 19/03/98

Cite this

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abstract = "Both, requirements for VHDL and restrictions to VHDL standards are discussed by many groups and forums. A problem to be solved is to handle the growing complexity of hardware designs and test environments. Aim of the paper is to support the discussion by defining requirements impacted by modern verification techniques. We focus on performance and modeling aspects from testbench development view. Therefore we consider simulation methodologies, coding styles and in particular VHDL extensions. Further, impacts on VHDL extensions by modern requirement engineering methodologies are dealt with.",

author = "Matthias Bauer and Wolfgang Ecker and Mike Heuchling",

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AU - Bauer, Matthias

AU - Ecker, Wolfgang

AU - Heuchling, Mike

PY - 1998

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AB - Both, requirements for VHDL and restrictions to VHDL standards are discussed by many groups and forums. A problem to be solved is to handle the growing complexity of hardware designs and test environments. Aim of the paper is to support the discussion by defining requirements impacted by modern verification techniques. We focus on performance and modeling aspects from testbench development view. Therefore we consider simulation methodologies, coding styles and in particular VHDL extensions. Further, impacts on VHDL extensions by modern requirement engineering methodologies are dealt with.

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M3 - Paper

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T2 - Proceedings of the 1998 International Verilog HDL Conference

Y2 - 16 March 1998 through 19 March 1998

ER -

VHDL 200× - requirements from testbench-view

Abstract

Conference

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