Verifying UML/OCL models using boolean satisfiability

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

123 Scopus citations

Abstract

Nowadays, modeling languages like UML are essential in the design of complex software systems and also start to enter the domain of hardware and hardware/software codesign. Due to shortening time-to-market demands, "first time right" requirements have thereby to be satisfied. In this paper, we propose an approach that makes use of Boolean satisfiability for verifying UML/OCL models. We describe how the respective components of a verification problem, namely system states of a UML model, OCL constraints, and the actual verification task, can be encoded and afterwards automatically solved using an off-the-shelf SAT solver. Experiments show that our approach can solve verification tasks significantly faster than previous methods while still supporting a large variety of UML/OCL constructs.

Original languageEnglish
Title of host publicationDATE 10 - Design, Automation and Test in Europe
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1341-1344
Number of pages4
ISBN (Print)9783981080162
DOIs
StatePublished - 2010
Externally publishedYes
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
Duration: 8 Mar 201012 Mar 2010

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

ConferenceDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010
Country/TerritoryGermany
CityDresden
Period8/03/1012/03/10

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