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Verification methods for VHDL RTL-subroutines
Wolfgang Ecker
Siemens AG
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peer-review
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Keyphrases
Performance Analysis
100%
Verification Method
100%
VHDL Code
100%
New Test Method
100%
Value Generation
100%
Logical Combination
100%
Logical Value
100%
HIL Simulation
100%
Engineering
Performance Analysis
100%
Test Method
100%
Reference Value
100%