Verification methods for VHDL RTL-subroutines

This article presents methods for the verification of RT-Level subroutines. Special emphasis lies on subroutines and operators of the VHDL standard synthesis packages, which are currently in the ballot phase. The methods are VHDL based only. Therefore they can be used for both verification of the synthesis package on different VHDL simulators and tests of simulator-built-in implementations of the package. Additionally, the resulting VHDL code can be used for performance analysis of different simulators. A set of approaches for stimuli and reference value generation, including new test methods for meta-logical values, and combinations of them are presented in the article.