Verfahren zur Logiksimulation und Laufzeitmodellierung in digitalen Schaltungen

This paper focuses on the modeling of the timing behavior of digital circuits in logic simulators. Based upon the well-known and flexible ambiguity delay model (min-max-delay), an algorithm for the accurate computation of ambiguously delayed waveforms is presented. The algorithm is clearly built on the concept of superposition and causality, whereby the behavior of the delay model can easily be predicted. Applications include design simulation hazard detection and timing verification. Part of a survey on event-driven simulation is a proposal for an efficient data-structure for event scheduling.