TY - GEN
T1 - Variation tolerant high resolution and low latency time-to-digital converter
AU - Henzler, S.
AU - Koeppe, S.
AU - Lorenz, D.
AU - Kamp, W.
AU - Kuenemund, R.
AU - Schmitt-Landsiedel, D.
PY - 2007
Y1 - 2007
N2 - A high resolution time-to-digital converter (TDC) with low latency and low deadtime is proposed. A coarse time quantization derived from a differential inverter delay line is locally interpolated with passive voltage dividers. The high resolution TDC is monotonie by construction which makes the concept very robust against process variations. The feasibility is demonstrated with an 8-bit TDC with a resolution of 0.25 inverter delays in a 90nm low power CMOS technology. The resolution limits imposed by clock uncertainty and local variations are derived theoretically.
AB - A high resolution time-to-digital converter (TDC) with low latency and low deadtime is proposed. A coarse time quantization derived from a differential inverter delay line is locally interpolated with passive voltage dividers. The high resolution TDC is monotonie by construction which makes the concept very robust against process variations. The feasibility is demonstrated with an 8-bit TDC with a resolution of 0.25 inverter delays in a 90nm low power CMOS technology. The resolution limits imposed by clock uncertainty and local variations are derived theoretically.
UR - https://www.scopus.com/pages/publications/44849100549
U2 - 10.1109/ESSCIRC.2007.4430278
DO - 10.1109/ESSCIRC.2007.4430278
M3 - Conference contribution
AN - SCOPUS:44849100549
SN - 1424411254
SN - 9781424411252
T3 - ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference
SP - 194
EP - 197
BT - ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference
T2 - ESSCIRC 2007 - 33rd European Solid-State Circuits Conference
Y2 - 11 September 2007 through 13 September 2007
ER -