Validating SystemC implementations against their formal specifications

Jannis Stoppe, Robert Wille, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

The ever increasing complexity of embedded systems leads to a constant strive for higher levels of abstraction. While the design at the Electronic System Level (ESL) with SystemC as the common programming language is state-of-theart today, also the use of formal specifications by means of modeling languages such as UML or SysML receives more and more attention. This raises the question of how to validate an ESL implementation against a given formal specification. For this, SystemC's limited introspection and reflection features pose a serious obstacle. In this paper, a methodology is presented that retrieves the necessary static and dynamic information which is needed in order to validate a SystemC design. For this purpose, we retrieve information from the SystemC API and compiler-generated debug symbols. The proposed solution can be applied to a wide variety of project setups and requires only minimal adjustments to retrieve the necessary information.

Original languageEnglish
Title of host publicationSBCCI 2014
Subtitle of host publicationProceedings of the 27th Symposium on Integrated Circuits and Systems Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479968732
DOIs
StatePublished - 19 Dec 2014
Externally publishedYes
Event27th Symposium on Integrated Circuits and Systems Design, SBCCI 2014 - Aracaju, Brazil
Duration: 1 Sep 20145 Sep 2014

Publication series

NameSBCCI 2014: Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

Conference

Conference27th Symposium on Integrated Circuits and Systems Design, SBCCI 2014
Country/TerritoryBrazil
CityAracaju
Period1/09/145/09/14

Keywords

  • Equivalence
  • SysML
  • SystemC
  • UML
  • Validation

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