Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists

Michael Tempelmeier; Maximilian Werner; Georg Sigl

doi:10.1109/HST.2019.8740843

Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists

Michael Tempelmeier, Maximilian Werner, Georg Sigl

Chair of Security in Information Technology

Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work, we present five optimised implementations on a Xilinx-Zynq7200 SoC for the high-speed and defence in depth finalists of the CAESAR competition for finding authenticated encryption ciphers. We eliminated the standard interfaces used during the competition. Through optimised interfaces between hardware and software, we were able to get both performance improvements as well as reduction in used programmable logic. The performance of our implementations is comparable to pure hardware implementations, but our implementations are 50% smaller. Compared to pure SW implementations we are 16 times faster. Comparing the different algorithms, we come to the conclusion that Colm allows the fastest implementation.

Original language	English
Title of host publication	Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	228-237
Number of pages	10
ISBN (Electronic)	9781538680643
DOIs	https://doi.org/10.1109/HST.2019.8740843
State	Published - May 2019
Event	2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019 - McLean, United States Duration: 6 May 2019 → 10 May 2019

Publication series

Name	Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019

Conference

Conference	2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019
Country/Territory	United States
City	McLean
Period	6/05/19 → 10/05/19

Access to Document

10.1109/HST.2019.8740843

Cite this

Tempelmeier, M., Werner, M., & Sigl, G. (2019). Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists. In Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019 (pp. 228-237). Article 8740843 (Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HST.2019.8740843

Tempelmeier, Michael ; Werner, Maximilian ; Sigl, Georg. / Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists. Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 228-237 (Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019).

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title = "Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists",

abstract = "In this work, we present five optimised implementations on a Xilinx-Zynq7200 SoC for the high-speed and defence in depth finalists of the CAESAR competition for finding authenticated encryption ciphers. We eliminated the standard interfaces used during the competition. Through optimised interfaces between hardware and software, we were able to get both performance improvements as well as reduction in used programmable logic. The performance of our implementations is comparable to pure hardware implementations, but our implementations are 50% smaller. Compared to pure SW implementations we are 16 times faster. Comparing the different algorithms, we come to the conclusion that Colm allows the fastest implementation.",

author = "Michael Tempelmeier and Maximilian Werner and Georg Sigl",

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language = "English",

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Tempelmeier, M, Werner, M & Sigl, G 2019, Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists. in Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019., 8740843, Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019, Institute of Electrical and Electronics Engineers Inc., pp. 228-237, 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019, McLean, United States, 6/05/19. https://doi.org/10.1109/HST.2019.8740843

Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists. / Tempelmeier, Michael; Werner, Maximilian; Sigl, Georg.
Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 228-237 8740843 (Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Tempelmeier M, Werner M, Sigl G. Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists. In Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 228-237. 8740843. (Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019). doi: 10.1109/HST.2019.8740843

Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists

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