Use of a cmos static memory array as a technology test vehicle

A static memory array is described for use as a test vehicle in CMOS process development. Design guidelines are given for a large operating range and good testability. Address paths are defined for efficient comparison of access time measurements and simulations. the functional yield of SRAMs is correlated with defect density results from test structures to identify the relevant yield limiting defects. It is shown that an SRAM is a suitable test vehicle for yield prediction of complex CMOS random logic circuits.