TY - GEN
T1 - Unlocking Flexible Silicon Dangling Bond Logic Designs on Alternative Silicon Orientations
AU - Ng, Samuel S.H.
AU - Drewniok, Jan
AU - Walter, Marcel
AU - Retallick, Jacob
AU - Wille, Robert
AU - Walus, Konrad
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - With the impending plateau of Moore's Law, the search for novel computational paradigms has intensified. Silicon dangling bond (SiDB) logic emerges as a promising avenue in this quest, leveraging the quantum-dot-like properties of SiDBs and atomically precise fabrication techniques to realize logic functions at the nanometer scale. Advances in computer-aided design (CAD) tools specialized for SiDB logic exploration have also opened the door to novel logic research from the gate- to application-level. This paper introduces a lattice vector formulation for SiDB logic designs on alternative silicon lattice orientations, enabling the exploration of logic gates on arbitrary lattice orientations and addressing the limitations of previous SiDB logic research confined to the H-Si(100)-2 ×1 surface. A comprehensive workflow for designing standard tile libraries compatible with design automation frameworks is proposed, facilitating the scaling of SiDB layouts to large-scale systems implementation on multiple lattice orientations. We demonstrate the proposed lattice vector representation and the library design workflow through a case study on the H-Si(111)-1×1 surface, showcasing the first logic gates designed for this orientation. This advancement opens new avenues for SiDB logic research, enabling rigorous evaluations of various lattice orientations for future logic design studies and experimental investigations.
AB - With the impending plateau of Moore's Law, the search for novel computational paradigms has intensified. Silicon dangling bond (SiDB) logic emerges as a promising avenue in this quest, leveraging the quantum-dot-like properties of SiDBs and atomically precise fabrication techniques to realize logic functions at the nanometer scale. Advances in computer-aided design (CAD) tools specialized for SiDB logic exploration have also opened the door to novel logic research from the gate- to application-level. This paper introduces a lattice vector formulation for SiDB logic designs on alternative silicon lattice orientations, enabling the exploration of logic gates on arbitrary lattice orientations and addressing the limitations of previous SiDB logic research confined to the H-Si(100)-2 ×1 surface. A comprehensive workflow for designing standard tile libraries compatible with design automation frameworks is proposed, facilitating the scaling of SiDB layouts to large-scale systems implementation on multiple lattice orientations. We demonstrate the proposed lattice vector representation and the library design workflow through a case study on the H-Si(111)-1×1 surface, showcasing the first logic gates designed for this orientation. This advancement opens new avenues for SiDB logic research, enabling rigorous evaluations of various lattice orientations for future logic design studies and experimental investigations.
UR - http://www.scopus.com/inward/record.url?scp=85203119967&partnerID=8YFLogxK
U2 - 10.1109/NANO61778.2024.10628802
DO - 10.1109/NANO61778.2024.10628802
M3 - Conference contribution
AN - SCOPUS:85203119967
T3 - Proceedings of the IEEE Conference on Nanotechnology
SP - 57
EP - 62
BT - 2024 IEEE 24th International Conference on Nanotechnology, NANO 2024
PB - IEEE Computer Society
T2 - 24th IEEE International Conference on Nanotechnology, NANO 2024
Y2 - 8 July 2024 through 11 July 2024
ER -