U-Net based zero-hour defect inspection of electronic components and semiconductors

Automated visual inspection is a popular way of detecting many kind of defects at PCBs and electronic components without intervening in the manufacturing process. In this work, we present a novel approach for anomaly detection of PCBs where a U-Net architecture performs binary anomalous region segmentation and DBSCAN algorithm detects and localizes individual defects. At training time, reference images are needed to create annotations of anomalous regions, whereas at test time references images are not needed anymore. The proposed approach is validated on DeepPCB dataset and our internal chip defect dataset. We have achieved 0.80 and 0.75 mean Intersection of Union (mIoU) scores on DeepPCB and chip defect datasets, respectively, which demonstrates the effectiveness of the proposed approach. Moreover, for optimized and reduced models with computational costs lower than one giga FLOP, mIoU scores of 0.65 and above are achieved justifying the suitability of the proposed approach for embedded and potentially real-time applications.