Transformative Hardware Design Following the Model-Driven Architecture Vision

Zhao Han; Gabriel Rutsch; Deyan Wang; Bowen Li; Sebastian Siegfried Prebeck; Daniela Sanchez Lopera; Keerthikumara Devarajegowda; Wolfgang Ecker

doi:10.1007/978-3-031-16818-5_3

Transformative Hardware Design Following the Model-Driven Architecture Vision

Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker

Computation, Information and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Despite the high configurability of IPs and hardware generators, code modifications are still required to introduce aspect-oriented instrumentation to satisfy emerging aspectual design requirements such as on-chip debug and functional safety. These code modifications escalate development, verification efforts, and deteriorate code reuse. This paper proposes a highly efficient transformative hardware design methodology that leverages graph-grammar-based model transformations. Following the proposed methodology, main design functionalities and aspectual instrumentation are separately developed, automatically integrated, and verified. To demonstrate the applicability, industrial SoCs were transformed to support on-chip debug. Compared to the manual RTL coding, the proposed transformative methodology needed less than 32x Lines of Code (LoC) to develop and integrate the aspectual instrumentation. In particular, our approach enables high code reusability, as the implementation of the transformation script is a one-time effort, and can be applied to all evaluated SoCs. This high LoC gain and code reuse promote the overall productivity of digital design.

Original language	English
Title of host publication	VLSI-SoC
Subtitle of host publication	Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Revised and Extended Selected Papers
Editors	Victor Grimblatt, Chip Hong Chang, Anupam Chattopadhyay, Ricardo Reis, Andrea Calimera
Publisher	Springer Science and Business Media Deutschland GmbH
Pages	49-70
Number of pages	22
ISBN (Print)	9783031168178
DOIs	https://doi.org/10.1007/978-3-031-16818-5_3
State	Published - 2022
Event	29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021 - Virtual, Online Duration: 4 Oct 2021 → 8 Oct 2021

Publication series

Name	IFIP Advances in Information and Communication Technology
Volume	661 IFIP
ISSN (Print)	1868-4238
ISSN (Electronic)	1868-422X

Conference

Conference	29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021
City	Virtual, Online
Period	4/10/21 → 8/10/21

Keywords

Aspect-oriented programming
Electronic design automation
Model-driven architecture

Access to Document

10.1007/978-3-031-16818-5_3

Cite this

Han, Z., Rutsch, G., Wang, D., Li, B., Prebeck, S. S., Lopera, D. S., Devarajegowda, K., & Ecker, W. (2022). Transformative Hardware Design Following the Model-Driven Architecture Vision. In V. Grimblatt, C. H. Chang, A. Chattopadhyay, R. Reis, & A. Calimera (Eds.), VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Revised and Extended Selected Papers (pp. 49-70). (IFIP Advances in Information and Communication Technology; Vol. 661 IFIP). Springer Science and Business Media Deutschland GmbH. https://doi.org/10.1007/978-3-031-16818-5_3

Han, Zhao ; Rutsch, Gabriel ; Wang, Deyan et al. / Transformative Hardware Design Following the Model-Driven Architecture Vision. VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Revised and Extended Selected Papers. editor / Victor Grimblatt ; Chip Hong Chang ; Anupam Chattopadhyay ; Ricardo Reis ; Andrea Calimera. Springer Science and Business Media Deutschland GmbH, 2022. pp. 49-70 (IFIP Advances in Information and Communication Technology).

@inproceedings{a46ba7cebd96449ab9edf160e184b61a,

title = "Transformative Hardware Design Following the Model-Driven Architecture Vision",

abstract = "Despite the high configurability of IPs and hardware generators, code modifications are still required to introduce aspect-oriented instrumentation to satisfy emerging aspectual design requirements such as on-chip debug and functional safety. These code modifications escalate development, verification efforts, and deteriorate code reuse. This paper proposes a highly efficient transformative hardware design methodology that leverages graph-grammar-based model transformations. Following the proposed methodology, main design functionalities and aspectual instrumentation are separately developed, automatically integrated, and verified. To demonstrate the applicability, industrial SoCs were transformed to support on-chip debug. Compared to the manual RTL coding, the proposed transformative methodology needed less than 32x Lines of Code (LoC) to develop and integrate the aspectual instrumentation. In particular, our approach enables high code reusability, as the implementation of the transformation script is a one-time effort, and can be applied to all evaluated SoCs. This high LoC gain and code reuse promote the overall productivity of digital design.",

keywords = "Aspect-oriented programming, Electronic design automation, Model-driven architecture",

author = "Zhao Han and Gabriel Rutsch and Deyan Wang and Bowen Li and Prebeck, {Sebastian Siegfried} and Lopera, {Daniela Sanchez} and Keerthikumara Devarajegowda and Wolfgang Ecker",

note = "Publisher Copyright: {\textcopyright} 2022, IFIP International Federation for Information Processing.; 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021 ; Conference date: 04-10-2021 Through 08-10-2021",

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Han, Z, Rutsch, G, Wang, D, Li, B, Prebeck, SS, Lopera, DS, Devarajegowda, K & Ecker, W 2022, Transformative Hardware Design Following the Model-Driven Architecture Vision. in V Grimblatt, CH Chang, A Chattopadhyay, R Reis & A Calimera (eds), VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology, vol. 661 IFIP, Springer Science and Business Media Deutschland GmbH, pp. 49-70, 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Virtual, Online, 4/10/21. https://doi.org/10.1007/978-3-031-16818-5_3

Transformative Hardware Design Following the Model-Driven Architecture Vision. / Han, Zhao; Rutsch, Gabriel; Wang, Deyan et al.
VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Revised and Extended Selected Papers. ed. / Victor Grimblatt; Chip Hong Chang; Anupam Chattopadhyay; Ricardo Reis; Andrea Calimera. Springer Science and Business Media Deutschland GmbH, 2022. p. 49-70 (IFIP Advances in Information and Communication Technology; Vol. 661 IFIP).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Devarajegowda, Keerthikumara

AU - Ecker, Wolfgang

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AB - Despite the high configurability of IPs and hardware generators, code modifications are still required to introduce aspect-oriented instrumentation to satisfy emerging aspectual design requirements such as on-chip debug and functional safety. These code modifications escalate development, verification efforts, and deteriorate code reuse. This paper proposes a highly efficient transformative hardware design methodology that leverages graph-grammar-based model transformations. Following the proposed methodology, main design functionalities and aspectual instrumentation are separately developed, automatically integrated, and verified. To demonstrate the applicability, industrial SoCs were transformed to support on-chip debug. Compared to the manual RTL coding, the proposed transformative methodology needed less than 32x Lines of Code (LoC) to develop and integrate the aspectual instrumentation. In particular, our approach enables high code reusability, as the implementation of the transformation script is a one-time effort, and can be applied to all evaluated SoCs. This high LoC gain and code reuse promote the overall productivity of digital design.

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Han Z, Rutsch G, Wang D, Li B, Prebeck SS, Lopera DS et al. Transformative Hardware Design Following the Model-Driven Architecture Vision. In Grimblatt V, Chang CH, Chattopadhyay A, Reis R, Calimera A, editors, VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Revised and Extended Selected Papers. Springer Science and Business Media Deutschland GmbH. 2022. p. 49-70. (IFIP Advances in Information and Communication Technology). doi: 10.1007/978-3-031-16818-5_3