Towards low-cost fault detection strategy of FPGA configuration memory in real-time systems

As a result of the recent advancements in technol-ogy, FPGAs are more often used for automotive applications. They must therefore meet industrial requirements like a fast and very low cost fault detection strategy for their configuration memory. Cyclic memory tests are the state of the art approach for this task. They do, however, violate fault detection times, especially for the latest FPGA devices. The approach presented in this paper splits the configuration memory in several parts and prioritizes their test execution depending on the application data flow. Using two conclusive examples this adaptive strategy is compared to state of the art memory tests on a Xilinx FPGA. They show that our approach is a useful means to efficiently meet requirements on automotive fault detection times.