@inproceedings{16a9027864ba4b4d97fee838dbcb904d,
title = "Towards line-aware realizations of expressions for HDL-based synthesis of reversible circuits",
abstract = "Hardware Description Languages (HDLs) allow for the efficient synthesis of large and complex circuits. Consequently, researchers also investigated their potential in the domain of reversible logic. Here, existing HDL-based synthesis approaches suffer from the significant drawback of employing additional circuit lines in order to buffer intermediate results. In this work, we investigate the possibility of reducing this overhead. For this purpose, an alternative synthesis scheme is proposed and evaluated which aims at a more efficient realization of expressions. The general idea is to re-compute (i.e to undo) sub-expressions as soon as the respective intermediate results are not needed anymore. The observations and discussions result in initial guidelines on how to realize expressions more efficiently as well as a better understanding of the potential of HDL-based synthesis.",
keywords = "Hardware description languages, Optimization, Reversible circuits, Synthesis",
author = "Zaid Al-Wardi and Robert Wille and Rolf Drechsler",
note = "Publisher Copyright: {\textcopyright} Springer International Publishing Switzerland 2015.; 7th International Conference on Reversible Computation, RC 2015 ; Conference date: 16-07-2015 Through 17-07-2015",
year = "2015",
doi = "10.1007/978-3-319-20860-2_15",
language = "English",
isbn = "9783319208596",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "233--247",
editor = "Jean Krivine and Jean-Bernard Stefani",
booktitle = "Reversible Computation - 7th International Conference, RC 2015, Proceedings",
}