Towards line-aware realizations of expressions for HDL-based synthesis of reversible circuits

Zaid Al-Wardi, Robert Wille, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Hardware Description Languages (HDLs) allow for the efficient synthesis of large and complex circuits. Consequently, researchers also investigated their potential in the domain of reversible logic. Here, existing HDL-based synthesis approaches suffer from the significant drawback of employing additional circuit lines in order to buffer intermediate results. In this work, we investigate the possibility of reducing this overhead. For this purpose, an alternative synthesis scheme is proposed and evaluated which aims at a more efficient realization of expressions. The general idea is to re-compute (i.e to undo) sub-expressions as soon as the respective intermediate results are not needed anymore. The observations and discussions result in initial guidelines on how to realize expressions more efficiently as well as a better understanding of the potential of HDL-based synthesis.

Original languageEnglish
Title of host publicationReversible Computation - 7th International Conference, RC 2015, Proceedings
EditorsJean Krivine, Jean-Bernard Stefani
PublisherSpringer Verlag
Pages233-247
Number of pages15
ISBN (Print)9783319208596
DOIs
StatePublished - 2015
Externally publishedYes
Event7th International Conference on Reversible Computation, RC 2015 - Grenoble, France
Duration: 16 Jul 201517 Jul 2015

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume9138
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference7th International Conference on Reversible Computation, RC 2015
Country/TerritoryFrance
CityGrenoble
Period16/07/1517/07/15

Keywords

  • Hardware description languages
  • Optimization
  • Reversible circuits
  • Synthesis

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