Towards HDL-based synthesis of reversible circuits with no additional lines

Reversible circuits are needed in different emerging technologies, but their design is still mainly conducted on low abstraction levels thus far. Hardware Description Languages (HDLs) provide suitable description means to lift the design process to higher levels of abstractions. However, synthesis of HDL descriptions thus far still relies on non-reversible building blocks even if the corresponding statements are purely reversible. This leads to reversible circuits with additional circuit lines (i.e., circuit signals)-rendering HDL-based synthesis infeasible for many applications such as quantum computing. In this work, we present a synthesis method which realizes many of the HDL statements with no additional lines at all. To this end, we consider the respective (reversible) HDL statements as an entirety rather than breaking it down into (possibly non-reversible) building blocks. For the first time, this allows to realize many HDL descriptions with no additional circuit lines.