TY - GEN
T1 - Towards dynamic cache and bandwidth invasion
AU - Tradowsky, Carsten
AU - Schreiber, Martin
AU - Vesper, Malte
AU - Domladovec, Ivan
AU - Braun, Maximilian
AU - Bungartz, Hans Joachim
AU - Becker, Jürgen
PY - 2014
Y1 - 2014
N2 - State-of-the-art optimizations for high performance are frequently related to particular hardware parameters and features. This typically leads to optimized software for execution on particular hardware configurations. However, so far, the applications lack the ability to modify hardware parameters either statically before execution of a program or dynamically during run-time. In this paper, we first propose to utilize the flexibility of underlying invasive hardware to adapt to the needs of the software. This enables us to ask for more than just processing power by, e.g., requesting particular cache parameters that correspond to certain application properties. The adaptive hardware architecture therefore is able to dynamically reconfigure itself dependent on the availability of the resources in order to achieve an optimized working point for each application scenario. Secondly, we present requirements for dynamical scheduling of computing resources to resource-competing applications. This becomes mandatory to account for memory-access characteristics of concurrently executed applications. We propose consideration of such characteristics with bandwidth-aware invasion. With this novel approach, we are able to show that dynamic hardware and software co-design leads to improved utilization of the underlying hardware resulting in higher throughput in means of efficiency such as application-throughput per time-unit.
AB - State-of-the-art optimizations for high performance are frequently related to particular hardware parameters and features. This typically leads to optimized software for execution on particular hardware configurations. However, so far, the applications lack the ability to modify hardware parameters either statically before execution of a program or dynamically during run-time. In this paper, we first propose to utilize the flexibility of underlying invasive hardware to adapt to the needs of the software. This enables us to ask for more than just processing power by, e.g., requesting particular cache parameters that correspond to certain application properties. The adaptive hardware architecture therefore is able to dynamically reconfigure itself dependent on the availability of the resources in order to achieve an optimized working point for each application scenario. Secondly, we present requirements for dynamical scheduling of computing resources to resource-competing applications. This becomes mandatory to account for memory-access characteristics of concurrently executed applications. We propose consideration of such characteristics with bandwidth-aware invasion. With this novel approach, we are able to show that dynamic hardware and software co-design leads to improved utilization of the underlying hardware resulting in higher throughput in means of efficiency such as application-throughput per time-unit.
KW - HPC
KW - adaptive
KW - application-specific microarchitecture
KW - compute-bound
KW - invasive computing
KW - memory-bound
KW - reconfigurable cache
UR - http://www.scopus.com/inward/record.url?scp=84958533084&partnerID=8YFLogxK
U2 - 10.1007/978-3-319-05960-0_9
DO - 10.1007/978-3-319-05960-0_9
M3 - Conference contribution
AN - SCOPUS:84958533084
SN - 9783319059594
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 97
EP - 107
BT - Reconfigurable Computing
PB - Springer Verlag
T2 - 10th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications, ARC 2014
Y2 - 14 April 2014 through 16 April 2014
ER -