Towards Automatic Hardware Synthesis from Formal Specification to Implementation

Fritjof Bornebusch, Christoph Luth, Robert Wille, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

In this work, we sketch an automated design flow for hardware synthesis based on a formal specification. Verification results are propagated from the FSL level through the proposed flow to generate an ESL model as well as an RTL implementation automatically. In contrast, the established design flow relies on manual implementations at the ESL and RTL level. The proposed design flow combines proof assistants with functional hardware description languages. This combination decreases the implementation effort significantly and the generation of test benches is no longer needed. We illustrate our design flow by specifying and synthesizing a set of benchmarks that contain sequential and combinational hardware designs. We compare them with implementations required by the established hardware design flow.

Original languageEnglish
Title of host publicationASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages375-380
Number of pages6
ISBN (Electronic)9781728141237
DOIs
StatePublished - Jan 2020
Externally publishedYes
Event25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020 - Beijing, China
Duration: 13 Jan 202016 Jan 2020

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2020-January

Conference

Conference25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020
Country/TerritoryChina
CityBeijing
Period13/01/2016/01/20

Fingerprint

Dive into the research topics of 'Towards Automatic Hardware Synthesis from Formal Specification to Implementation'. Together they form a unique fingerprint.

Cite this