TY - GEN
T1 - Towards Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2×1 Surface
AU - Walter, Marcel
AU - Croshaw, Jeremiah
AU - Hang Ng, Samuel Sze
AU - Walus, Konrad
AU - Wolkow, Robert
AU - Wille, Robert
N1 - Publisher Copyright:
© 2024 EDAA.
PY - 2024
Y1 - 2024
N2 - Recent advancements in Silicon Dangling Bond (SiDB) fabrication have transitioned from manual to automated processes. However, sub-nanometer substrate defects remain a significant challenge, thus preventing the fabrication of functional logic. Current design automation techniques lack defect-aware strategies. This paper introduces an idea for a surface defect model based on experimentally verified defects, which can be applied to enhance the robustness of established gate libraries. Additionally, a prototypical automatic placement and routing algorithm is presented, utilizing STM data from physical experiments to obtain dot- accurate circuitry resilient to atomic surface defects. Initial evaluations on surfaces with varying defect rates demonstrate their critical impact, suggesting that fabrication processes must achieve defect rates of around 0.1 % to further advance this circuit technology.
AB - Recent advancements in Silicon Dangling Bond (SiDB) fabrication have transitioned from manual to automated processes. However, sub-nanometer substrate defects remain a significant challenge, thus preventing the fabrication of functional logic. Current design automation techniques lack defect-aware strategies. This paper introduces an idea for a surface defect model based on experimentally verified defects, which can be applied to enhance the robustness of established gate libraries. Additionally, a prototypical automatic placement and routing algorithm is presented, utilizing STM data from physical experiments to obtain dot- accurate circuitry resilient to atomic surface defects. Initial evaluations on surfaces with varying defect rates demonstrate their critical impact, suggesting that fabrication processes must achieve defect rates of around 0.1 % to further advance this circuit technology.
UR - http://www.scopus.com/inward/record.url?scp=85196494159&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:85196494159
T3 - Proceedings -Design, Automation and Test in Europe, DATE
BT - 2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024
Y2 - 25 March 2024 through 27 March 2024
ER -