Towards a generic verification methodology for system models

Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

The use of modeling languages such as UML or SysML enables to formally specify and verify the behavior of digital systems already in the absence of a specific implementation. However, for each modeling method and verification task usually a separate verification solution has to be applied today. In this paper, a methodology is envisioned that aims at stopping this "inflation" of different verification approaches and instead employs a generic methodology. For this purpose, a given specification as well as the verification shall be transformed into a basic model which itself is specified by means of a generic modeling language. Then, a range of automatic reasoning engines shall uniformly be applied to perform the actual verification. A feasibility study demonstrates the applicability of the envisioned approach.

Original languageEnglish
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1193-1196
Number of pages4
ISBN (Print)9783981537000
DOIs
StatePublished - 2013
Externally publishedYes
Event16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France
Duration: 18 Mar 201322 Mar 2013

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

Conference16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
Country/TerritoryFrance
CityGrenoble
Period18/03/1322/03/13

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