@inproceedings{c2729bf45b6749faabc9b8b0cae82f76,
title = "Topology optimization techniques for power/ground networks in VLSI",
abstract = "In this paper we present two methods for optimizing the topology of given power/ground networks on VLSI chips. The cycle-reduction-method removes cycles and root paths (paths between two pads) in a general power/ground graph. The node-reduction-method removes branching nodes (nodes incident to more than two branches) in a power/ground tree. Both methods yield a reduction of the power/ground routing area and do not deteriorate the reliability of the power/ground network. We include small examples to explain our procedures and present experimental results for benchmark circuits.",
author = "Erhard, \{K. H.\} and Johannes, \{F. M.\} and R. Dachauer",
year = "1992",
language = "English",
isbn = "0818627808",
series = "European Design Automation Conference",
publisher = "Publ by IEEE",
pages = "362--367",
booktitle = "European Design Automation Conference",
note = "European Design Automation Conference -EURO-VHDL '92 ; Conference date: 07-09-1992 Through 10-09-1992",
}