Timing violations due to vDD/VSS bounce

M. Eireiner; S. Henzler; J. Berthold; C. Pacha; G. Georgakos; D. Schmitt-Landsiedel

doi:10.5194/ars-4-197-2006

Timing violations due to v_DD/V_SS bounce

M. Eireiner
, S. Henzler
, J. Berthold
, C. Pacha
, G. Georgakos
, D. Schmitt-Landsiedel

Medicine and Health

Technical University of Munich
Infineon Technologies AG

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.

Original language	English
Pages (from-to)	197-205
Number of pages	9
Journal	Advances in Radio Science
Volume	4
DOIs	https://doi.org/10.5194/ars-4-197-2006
State	Published - 2006

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title = "Timing violations due to vDD/VSS bounce",

abstract = "The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.",

author = "M. Eireiner and S. Henzler and J. Berthold and C. Pacha and G. Georgakos and D. Schmitt-Landsiedel",

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T1 - Timing violations due to vDD/VSS bounce

AU - Eireiner, M.

AU - Henzler, S.

AU - Berthold, J.

AU - Pacha, C.

AU - Georgakos, G.

AU - Schmitt-Landsiedel, D.

PY - 2006

Y1 - 2006

N2 - The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.

AB - The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.

UR - https://www.scopus.com/pages/publications/33748540376

U2 - 10.5194/ars-4-197-2006

DO - 10.5194/ars-4-197-2006

M3 - Article

AN - SCOPUS:33748540376

SN - 1684-9965

VL - 4

SP - 197

EP - 205

JO - Advances in Radio Science

JF - Advances in Radio Science

ER -

Timing violations due to v_DD/V_SS bounce

Abstract

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