Timing violations due to vDD/VSS bounce

M. Eireiner, S. Henzler, J. Berthold, C. Pacha, G. Georgakos, D. Schmitt-Landsiedel

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.

Original languageEnglish
Pages (from-to)197-205
Number of pages9
JournalAdvances in Radio Science
Volume4
DOIs
StatePublished - 2006

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