Abstract
The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.
Original language | English |
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Pages (from-to) | 197-205 |
Number of pages | 9 |
Journal | Advances in Radio Science |
Volume | 4 |
DOIs | |
State | Published - 2006 |