Timing Resilience for Efficient and Secure Circuits

Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl, Ulf Schlichtmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


In this paper, we will cover several techniques that can enhance the resilience of timing of digital circuits. Using post-silicon tuning components, the clock arrival times at flip-flops can be modified after manufacturing to balance delays between flip-flops. The actual delay properties of flip-flops will be examined to exploit the natural flexibility of such components. Wave-pipelining paths spanning several flip-flop stages can be integrated into a synchronous design to improve the circuit performance and to reduce area. In addition, with this technique, it cannot be taken for granted anymore that all the combinational paths in a circuit work with respect to one clock period. Therefore, a netlist alone does not represent all the design information. This feature enables the potential to embed wave-pipelining paths into a circuit to increase the complexity of reverse engineering. In order to replicate a design, attackers therefore have to identify the locations of the wave-pipelining paths, in addition to the netlist extracted from reverse engineering. Therefore, the security of the circuit against counterfeiting can be improved.

Original languageEnglish
Title of host publicationASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)9781728141237
StatePublished - Jan 2020
Event25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020 - Beijing, China
Duration: 13 Jan 202016 Jan 2020

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC


Conference25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020


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