Timing driven placement in interaction with netlist transformations

In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations are integrated into the placement process, an accurate net delay model is available. This model provides the basis for effective netlist transformations. In contrast to previous approaches that apply netlist transformations during placement, we are not restricted to local transformations like fanout buffering or gate resizing. Instead, we exploit global dependencies between the signals in the circuit. Results for benchmark circuits show excellent placement quality. The maximum path delay is reduced up to 33% compared to the initial timing driven placement of the original netlist and up to 18% compared to the results obtained by consecutive optimization of the netlist and timing driven placement of the optimized netlist. This delay reduction is achieved with almost no increase in chip area.