Abstract
Many authors have shown how to break the AES cryptographic algorithm with side channel attacks; specially the timing attacks oriented to caches, like Prime+Probe. In this paper, we present two practical timing attacks on NoC that improve Prime+Probe technique, the P+P Firecracker, and P+P Arrow. Our attacks target the communication between an ARM Cortex-A9 core and a shared cache memory. Furthermore, we evaluate a secure enhanced NoC as a countermeasure against the timing attack. Finally, we demonstrate that attacks on MPSoCs through the NoC are a real threat and need to be further explored.
| Original language | English |
|---|---|
| Pages (from-to) | 556-565 |
| Number of pages | 10 |
| Journal | Microprocessors and Microsystems |
| Volume | 52 |
| DOIs | |
| State | Published - Jul 2017 |
Keywords
- Network-on-Chip
- Security NoC
- Timing attack
- Timing side-channel attack
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