TY - JOUR
T1 - Timing attack on NoC-based systems
T2 - Prime+Probe attack and NoC-based protection
AU - Reinbrecht, Cezar
AU - Susin, Altamiro
AU - Bossuet, Lilian
AU - Sigl, Georg
AU - Sepúlveda, Johanna
N1 - Publisher Copyright:
© 2017 Elsevier B.V.
PY - 2017/7
Y1 - 2017/7
N2 - Many authors have shown how to break the AES cryptographic algorithm with side channel attacks; specially the timing attacks oriented to caches, like Prime+Probe. In this paper, we present two practical timing attacks on NoC that improve Prime+Probe technique, the P+P Firecracker, and P+P Arrow. Our attacks target the communication between an ARM Cortex-A9 core and a shared cache memory. Furthermore, we evaluate a secure enhanced NoC as a countermeasure against the timing attack. Finally, we demonstrate that attacks on MPSoCs through the NoC are a real threat and need to be further explored.
AB - Many authors have shown how to break the AES cryptographic algorithm with side channel attacks; specially the timing attacks oriented to caches, like Prime+Probe. In this paper, we present two practical timing attacks on NoC that improve Prime+Probe technique, the P+P Firecracker, and P+P Arrow. Our attacks target the communication between an ARM Cortex-A9 core and a shared cache memory. Furthermore, we evaluate a secure enhanced NoC as a countermeasure against the timing attack. Finally, we demonstrate that attacks on MPSoCs through the NoC are a real threat and need to be further explored.
KW - Network-on-Chip
KW - Security NoC
KW - Timing attack
KW - Timing side-channel attack
UR - http://www.scopus.com/inward/record.url?scp=85011016534&partnerID=8YFLogxK
U2 - 10.1016/j.micpro.2016.12.010
DO - 10.1016/j.micpro.2016.12.010
M3 - Article
AN - SCOPUS:85011016534
SN - 0141-9331
VL - 52
SP - 556
EP - 565
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
ER -