Timing analysis of Esterel programs on general-purpose multiprocessors

Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations


Synchronous languages like Esterel have gained wide popularity in certain domains such as avionics. However, platform-specific timing analysis of code generated from Esterel-like specifications have mostly been neglected so far. The growing volume of electronics and software in domains like automotive, calls for formalspecification based code generation to replace manually written and optimized code. Such cost-sensitive domains require tight estimation of timing properties of the generated code. Towards this goal, we propose a scheme for generating C code from Esterel specifications for a multiprocessor platform, followed by timing analysis of the generated code. Due to dependencies across program fragments mapped onto different processors, traditional Worst-Case Execution Time (WCET) analysis techniques for sequential programs cannot applied be to this setting. Our proposed timing analysis technique is tailored to capture such inter-processor code dependencies. Our main novelty stems from how we detect and remove infeasible paths arising from a multiprocessor implementation during our timing analysis. We apply our timing analysis on a number of standard Esterel benchmarks, which show that performing the proposed inter-processor infeasible path elimination may lead to up to 14.3% tighter estimation of the WCRT, thereby leading to resource over-dimensioning and poor design.

Original languageEnglish
Title of host publicationProceedings of the 47th Design Automation Conference, DAC '10
Number of pages4
StatePublished - 2010
Event47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
Duration: 13 Jun 201018 Jun 2010

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Conference47th Design Automation Conference, DAC '10
Country/TerritoryUnited States
CityAnaheim, CA


  • Esterel
  • Multiprocessor
  • Synchronous language
  • Timing analysis


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