Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations

Logic Built-In Self-Test (LBIST) with stored deterministic patterns is supported by the major CAD vendors and is gaining increasing attention, especially for safety-critical applications such as automotive. It is used for both manufacturing and periodic in-field testing. An unresolved challenge so far stems from the inevitable process variations. This paper presents the first approach for storage-based BIST addressing delay faults under process variations and multiple voltages. A unified solution for pattern generation, test set compaction and BIST hardware is presented that is compatible with commercial schemes. The solution significantly outperforms traditional N-detect for transition faults in terms of test set size, test application time and fault efficiency.