TY - JOUR
T1 - Three-level ZVS active clamping PWM for the DC-DC buck converter
AU - Rodrigues, Jean Paulo
AU - Mussa, Samir Ahmad
AU - Heldwein, Marcelo Lobo
AU - Perin, Arnaldo José
N1 - Funding Information:
Manuscript received December 5, 2008; revised March 23, 2009. Current version published September 2, 2009. This work was supported in part by the National Counsel of Technological and Scientific Development (CNPq), Brazil. Recommended for publication by Associate Editor M. Ferdowsi.
PY - 2009
Y1 - 2009
N2 - This paper presents the study of a dc-dc buck converter with three-level buck clamping (buck-buck), zero-voltage switching (ZVS), active clamping, and constant-frequency pulsewidth modulation (PWM). Other ZVS dc-dc converter topologies that employ three-level switching cells are introduced, and their steady-state dc gain is analyzed. This analysis shows that the buck-buck converter has characteristics that warrant a more detailed study. A feature that is common to all the introduced topologies is the theoretical reduction of the voltage stresses across the active semiconductors to 50% of the corresponding two-level converters. Accordingly, the switches of the buck-buck converter provide 50% of the blocking voltage of a ZVS two-level buck converter. The steady-state analysis of the converter is performed according to the description of the operation stages of the converter. Based on the performed analyses, a comparative discussion to other topologies is given. Furthermore, a topologic derivation of the circuit is presented, which provides ZVS operation to all semiconductors. Finally, a simplified design procedure is proposed, and used to design and build a prototype. Experimental results from a laboratory prototype are presented.
AB - This paper presents the study of a dc-dc buck converter with three-level buck clamping (buck-buck), zero-voltage switching (ZVS), active clamping, and constant-frequency pulsewidth modulation (PWM). Other ZVS dc-dc converter topologies that employ three-level switching cells are introduced, and their steady-state dc gain is analyzed. This analysis shows that the buck-buck converter has characteristics that warrant a more detailed study. A feature that is common to all the introduced topologies is the theoretical reduction of the voltage stresses across the active semiconductors to 50% of the corresponding two-level converters. Accordingly, the switches of the buck-buck converter provide 50% of the blocking voltage of a ZVS two-level buck converter. The steady-state analysis of the converter is performed according to the description of the operation stages of the converter. Based on the performed analyses, a comparative discussion to other topologies is given. Furthermore, a topologic derivation of the circuit is presented, which provides ZVS operation to all semiconductors. Finally, a simplified design procedure is proposed, and used to design and build a prototype. Experimental results from a laboratory prototype are presented.
KW - Buck
KW - Dc-dc converter
KW - Pulsewidth modulation (PWM)
KW - Soft switching
KW - Three levels
UR - http://www.scopus.com/inward/record.url?scp=70349128172&partnerID=8YFLogxK
U2 - 10.1109/TPEL.2009.2022535
DO - 10.1109/TPEL.2009.2022535
M3 - Article
AN - SCOPUS:70349128172
SN - 0885-8993
VL - 24
SP - 2249
EP - 2258
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 10
ER -