TY - GEN
T1 - The System Verification Methodology for advanced TLM verification
AU - Oliveira, Marcio F.S.
AU - Haedicke, Finn
AU - Drechsler, Rolf
AU - Kuznik, Christoph
AU - Le, Hoang M.
AU - Ecker, Wolfgang
AU - Mueller, Wolfgang
AU - Große, Daniel
AU - Esen, Volkan
PY - 2012
Y1 - 2012
N2 - The IEEE-1800 SystemVerilog [20] system description and verification language integrates dedicated verification features, like constraint random stimulus generation and functional coverage, which are the building blocks of the Universal Verification Methodology (UVM) [3], the emerging standard for electronic systems verification. In this article, we introduce our System Verification Methodology (SVM) as a SystemC library for advanced Transaction Level Modeling (TLM) testbench implementation. As such, we first present SystemC libraries for the support of verification features like functional coverage and constrained random stimulus generation. Thereafter, we introduce the SVM with advanced TLM support based on SystemC and compare it to UVM and related approaches. Finally, we demonstrate the application of our SVM by means of a testbench for a two wheel self-balancing electric vehicle.
AB - The IEEE-1800 SystemVerilog [20] system description and verification language integrates dedicated verification features, like constraint random stimulus generation and functional coverage, which are the building blocks of the Universal Verification Methodology (UVM) [3], the emerging standard for electronic systems verification. In this article, we introduce our System Verification Methodology (SVM) as a SystemC library for advanced Transaction Level Modeling (TLM) testbench implementation. As such, we first present SystemC libraries for the support of verification features like functional coverage and constrained random stimulus generation. Thereafter, we introduce the SVM with advanced TLM support based on SystemC and compare it to UVM and related approaches. Finally, we demonstrate the application of our SVM by means of a testbench for a two wheel self-balancing electric vehicle.
KW - Constrained random stimulus generation
KW - Functional coverage
KW - SystemC
KW - SystemVerilog
KW - UVM
UR - http://www.scopus.com/inward/record.url?scp=84869049273&partnerID=8YFLogxK
U2 - 10.1145/2380445.2380497
DO - 10.1145/2380445.2380497
M3 - Conference contribution
AN - SCOPUS:84869049273
SN - 9781450314268
T3 - CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK
SP - 313
EP - 322
BT - CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK
T2 - 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, CODES+ISSS 2012, Co-located with 8th Embedded Systems Week, ESWEEK 2012
Y2 - 7 October 2012 through 12 October 2012
ER -