TY - GEN
T1 - The next generation of virtual prototyping
T2 - 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
AU - Bringmann, Oliver
AU - Ecker, Wolfgang
AU - Gerstlauer, Andreas
AU - Goyal, Ajay
AU - Mueller-Gritschneder, Daniel
AU - Sasidharan, Prasanth
AU - Singh, Simranjit
N1 - Publisher Copyright:
© 2015 EDAA.
PY - 2015/4/22
Y1 - 2015/4/22
N2 - Virtual Prototypes (VPs) have been now widely adopted by industry as platforms for early SW development, HW/SW co-verification, performance analysis and architecture exploration. Yet, rising design complexity, the need to test an increasing amount of software functionality as well as the verification of timing properties pose a growing challenge in the application of VPs. New approaches overcome the accuracy-speed bottleneck of today's virtual prototyping methods. These next-generation VPs are centered around ultra-fast host-compiled software models. Accuracy is obtained by advanced methods, which reconstruct the execution times of the software and model the timing behavior of the operating system, target processor and memory system. It is shown that simulation speed can further be increased by abstract TLM-based communication models and efficient hardware peripheral models. Additionally, an industrial flow for efficient model development is outlined. This support of ultra-fast and accurate HW/SW co-simulation will be a key enabler for successfully developing tomorrow's multiprocessor system-on-chip (MPSoC) platforms.
AB - Virtual Prototypes (VPs) have been now widely adopted by industry as platforms for early SW development, HW/SW co-verification, performance analysis and architecture exploration. Yet, rising design complexity, the need to test an increasing amount of software functionality as well as the verification of timing properties pose a growing challenge in the application of VPs. New approaches overcome the accuracy-speed bottleneck of today's virtual prototyping methods. These next-generation VPs are centered around ultra-fast host-compiled software models. Accuracy is obtained by advanced methods, which reconstruct the execution times of the software and model the timing behavior of the operating system, target processor and memory system. It is shown that simulation speed can further be increased by abstract TLM-based communication models and efficient hardware peripheral models. Additionally, an industrial flow for efficient model development is outlined. This support of ultra-fast and accurate HW/SW co-simulation will be a key enabler for successfully developing tomorrow's multiprocessor system-on-chip (MPSoC) platforms.
UR - http://www.scopus.com/inward/record.url?scp=84945903865&partnerID=8YFLogxK
U2 - 10.7873/date.2015.1105
DO - 10.7873/date.2015.1105
M3 - Conference contribution
AN - SCOPUS:84945903865
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1698
EP - 1707
BT - Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 March 2015 through 13 March 2015
ER -