The next frontier in IC design: Determining (and optimizing) robustness and resilience of integrated circuits and systems

Traditionally, designers of integrated circuits (ICs) and systems focused primarily on ensuring correct functionality of an IC, while meeting timing, power and area targets. Robustness and resilience of the resulting designs was taken for granted, assuming that the ICs were used within their stated specification range. However, two questions typically remained open: firstly, how much margin an IC design had before it would fail. E.g., when supply voltage Vdd dropped below its specified lower boundary, would the circuit fail immediately, or could it withstand a certain voltage drop? Secondly, how would faults on technology or transistor level impact system behavior? Not all faults will necessarily cause a system malfunction. Many faults might instead be masked on some level. How will various approaches to harden a system at a low level affect system resilience? These questions are best answered by novel cross-layer approaches. We discuss two approaches to address these questions. For the case of particle-induced soft errors in memory, we demonstrate an efficient approach to evaluate their impact on system level and to compare the cost-vs-benefit ratio of various hardening techniques. In addition, a broadly applicable approach to quantify the robustness of an IC will be presented. This approach supports the robustness comparison of different implementations for a given specification. It will be demonstrated exemplarily for timing robustness.