TY - GEN
T1 - The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping
AU - Mueller-Gritschneder, Daniel
AU - Devarajegowda, Keerthikumara
AU - DIttrich, Martin
AU - Ecker, Wolfgang
AU - Greim, Marc
AU - Schlichtmann, Ulf
N1 - Publisher Copyright:
© 2017 ACM.
PY - 2017/10/19
Y1 - 2017/10/19
N2 - This paper describes the Extendable Translating Instruction Set Simulator (ETISS). In addition to binary translation, ETISS features a plugin mechanism that allows to quickly include new functionality into the translation stage, the simulation loop, during accesses to the memory or whenever an interrupt is received. ETISS targets to become an advanced industrial-strength ISS with special focus on virtual prototypes (VPs) written in SystemC/TLM. In this paper, we will show examples of ETISS Plugins which include tracing tools, SystemC interfaces, closey-coupled peripherals or triggers for fault injection. A major drawback of developing a new binary translator such as ETISS is its lack of support for a variety of instruction set architectures (ISAs). At the moment ETISS supports the open-source OpenRISC orlk and partly RISC-V ISAs. Yet, in order to overcome this problem, we developed a toolchain to generate the binary translation stage for different ISAs following the MDA concept based on meta-modeling and code generation. It is planned to make ETISS available as an open-source tool to the research community.
AB - This paper describes the Extendable Translating Instruction Set Simulator (ETISS). In addition to binary translation, ETISS features a plugin mechanism that allows to quickly include new functionality into the translation stage, the simulation loop, during accesses to the memory or whenever an interrupt is received. ETISS targets to become an advanced industrial-strength ISS with special focus on virtual prototypes (VPs) written in SystemC/TLM. In this paper, we will show examples of ETISS Plugins which include tracing tools, SystemC interfaces, closey-coupled peripherals or triggers for fault injection. A major drawback of developing a new binary translator such as ETISS is its lack of support for a variety of instruction set architectures (ISAs). At the moment ETISS supports the open-source OpenRISC orlk and partly RISC-V ISAs. Yet, in order to overcome this problem, we developed a toolchain to generate the binary translation stage for different ISAs following the MDA concept based on meta-modeling and code generation. It is planned to make ETISS available as an open-source tool to the research community.
KW - ISA
KW - RISC-V
KW - code generation
KW - instruction set simulator
UR - http://www.scopus.com/inward/record.url?scp=85042070956&partnerID=8YFLogxK
U2 - 10.1145/3130265.3138858
DO - 10.1145/3130265.3138858
M3 - Conference contribution
AN - SCOPUS:85042070956
T3 - Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP
SP - 79
EP - 84
BT - Proceedings of the 2017 28th International Symposium on Rapid System Prototyping
PB - IEEE Computer Society
T2 - 2017 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017
Y2 - 19 October 2017 through 20 October 2017
ER -