The 65nm Tunneling Field Effect Transistor (TFET) 0.68 μm2 6T memory cell and multi-Vth device

Th Nirschl; St Henzler; J. Fischer; A. Bargagli-Stoffi; M. Fulde; M. Sterkel; P. Teichmann; U. Schaper; J. Einfeld; C. Linnenbank; J. Sedlmeir; C. Weber; R. Heinrich; M. Ostermayr; A. Olbrich; B. Dobler; E. Ruderer; R. Kakoschke; K. Schrüfer; G. Georgakos; W. Hansch; D. Schmitt-Landsiedel

doi:10.1109/ESSDER.2005.1546613

The 65nm Tunneling Field Effect Transistor (TFET) 0.68 μm² 6T memory cell and multi-V_th device

Th Nirschl
, St Henzler
, J. Fischer
, A. Bargagli-Stoffi
, M. Fulde
, M. Sterkel
, P. Teichmann
, U. Schaper
, J. Einfeld
, C. Linnenbank
, J. Sedlmeir
, C. Weber
, R. Heinrich
, M. Ostermayr
, A. Olbrich
, B. Dobler
, E. Ruderer
, R. Kakoschke
, K. Schrüfer
, G. Georgakos

W. Hansch, D. Schmitt-Landsiedel

Medicine and Health

Technical University of Munich
Infineon Technologies AG

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

The Tunneling Field Effect Transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550/μA/μm which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a System-on-a-Chip design is reduced by more than 5%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68μm² 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3%.

Original language	English
Title of host publication	Proceedings of ESSDERC 2005
Subtitle of host publication	35th European Solid-State Device Research Conference
Pages	173-176
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDER.2005.1546613
State	Published - 2005
Event	ESSDERC 2005: 35th European Solid-State Device Research Conference - Grenoble, France Duration: 12 Sep 2005 → 16 Sep 2005

Publication series

Name	Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference
Volume	2005

Conference

Conference	ESSDERC 2005: 35th European Solid-State Device Research Conference
Country/Territory	France
City	Grenoble
Period	12/09/05 → 16/09/05

Access to Document

10.1109/ESSDER.2005.1546613

Cite this

Nirschl, T., Henzler, S., Fischer, J., Bargagli-Stoffi, A., Fulde, M., Sterkel, M., Teichmann, P., Schaper, U., Einfeld, J., Linnenbank, C., Sedlmeir, J., Weber, C., Heinrich, R., Ostermayr, M., Olbrich, A., Dobler, B., Ruderer, E., Kakoschke, R., Schrüfer, K., ... Schmitt-Landsiedel, D. (2005). The 65nm Tunneling Field Effect Transistor (TFET) 0.68 μm² 6T memory cell and multi-V_th device. In Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference (pp. 173-176). Article 1546613 (Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference; Vol. 2005). https://doi.org/10.1109/ESSDER.2005.1546613

@inproceedings{9b0896c6dac64be0a17f09235849449c,

title = "The 65nm Tunneling Field Effect Transistor (TFET) 0.68 μm2 6T memory cell and multi-Vth device",

abstract = "The Tunneling Field Effect Transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550/μA/μm which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a System-on-a-Chip design is reduced by more than 5\%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68μm2 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3\%.",

author = "Th Nirschl and St Henzler and J. Fischer and A. Bargagli-Stoffi and M. Fulde and M. Sterkel and P. Teichmann and U. Schaper and J. Einfeld and C. Linnenbank and J. Sedlmeir and C. Weber and R. Heinrich and M. Ostermayr and A. Olbrich and B. Dobler and E. Ruderer and R. Kakoschke and K. Schr{\"u}fer and G. Georgakos and W. Hansch and D. Schmitt-Landsiedel",

year = "2005",

doi = "10.1109/ESSDER.2005.1546613",

language = "English",

isbn = "0780392035",

series = "Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference",

pages = "173--176",

booktitle = "Proceedings of ESSDERC 2005",

note = "ESSDERC 2005: 35th European Solid-State Device Research Conference ; Conference date: 12-09-2005 Through 16-09-2005",

}

Nirschl, T, Henzler, S, Fischer, J, Bargagli-Stoffi, A, Fulde, M, Sterkel, M, Teichmann, P, Schaper, U, Einfeld, J, Linnenbank, C, Sedlmeir, J, Weber, C, Heinrich, R, Ostermayr, M, Olbrich, A, Dobler, B, Ruderer, E, Kakoschke, R, Schrüfer, K, Georgakos, G, Hansch, W & Schmitt-Landsiedel, D 2005, The 65nm Tunneling Field Effect Transistor (TFET) 0.68 μm² 6T memory cell and multi-V_th device. in Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference., 1546613, Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference, vol. 2005, pp. 173-176, ESSDERC 2005: 35th European Solid-State Device Research Conference, Grenoble, France, 12/09/05. https://doi.org/10.1109/ESSDER.2005.1546613

The 65nm Tunneling Field Effect Transistor (TFET) 0.68 μm² 6T memory cell and multi-V_th device. / Nirschl, Th; Henzler, St; Fischer, J. et al.
Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference. 2005. p. 173-176 1546613 (Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Nirschl, Th

AU - Henzler, St

AU - Fischer, J.

AU - Bargagli-Stoffi, A.

AU - Fulde, M.

AU - Sterkel, M.

AU - Teichmann, P.

AU - Schaper, U.

AU - Einfeld, J.

AU - Linnenbank, C.

AU - Sedlmeir, J.

AU - Weber, C.

AU - Heinrich, R.

AU - Ostermayr, M.

AU - Olbrich, A.

AU - Dobler, B.

AU - Ruderer, E.

AU - Kakoschke, R.

AU - Schrüfer, K.

AU - Georgakos, G.

AU - Hansch, W.

AU - Schmitt-Landsiedel, D.

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N2 - The Tunneling Field Effect Transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550/μA/μm which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a System-on-a-Chip design is reduced by more than 5%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68μm2 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3%.

AB - The Tunneling Field Effect Transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550/μA/μm which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a System-on-a-Chip design is reduced by more than 5%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68μm2 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3%.

UR - https://www.scopus.com/pages/publications/33751413764

U2 - 10.1109/ESSDER.2005.1546613

DO - 10.1109/ESSDER.2005.1546613

M3 - Conference contribution

AN - SCOPUS:33751413764

SN - 0780392035

SN - 9780780392038

T3 - Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

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BT - Proceedings of ESSDERC 2005

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Nirschl T, Henzler S, Fischer J, Bargagli-Stoffi A, Fulde M, Sterkel M et al. The 65nm Tunneling Field Effect Transistor (TFET) 0.68 μm² 6T memory cell and multi-V_th device. In Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference. 2005. p. 173-176. 1546613. (Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference). doi: 10.1109/ESSDER.2005.1546613