Technology Mapping for Cryogenic CMOS Circuits

Cryogenic CMOS circuits have garnered significant attention for their potential applications in fields such as quantum computing, magnetic resonance imaging, particle detectors, and space missions. Operating at temperatures below 77 K down to almost absolute zero, these circuits face stringent power constraints due to the limited cooling power available at deep cryogenic temperatures. While cryogenic operation can substantially reduce leakage current and improve transistor efficiency, it is crucial to optimize cryogenic CMOS circuits for minimal static and dynamic power consumption to operate within the cooling constraints. In this paper, we present a cryogenic-aware technology mapping approach to optimize the power characteristics of cryogenic CMOS circuits. The proposed method takes a technology-independent logic network and a cryogenic standard-cell library as input and produces a technology-mapped gate-level netlist with significantly reduced power consumption. By considering static and dynamic power constraints at cryogenic temperatures, the approach achieves up to a 26.89 % average reduction in power consumption compared to a state-of-the-art cryogenic-unaware algorithm. This optimization enables large-scale standard-cell-based digital circuits to operate efficiently at cryogenic temperatures in crucial applications.