Technology and circuit optimization of resistive RAM for low-power, reproducible operation

D. C. Sekar; B. Bateman; U. Raghuram; S. Bowyer; Y. Bai; M. Calarrudo; P. Swab; J. Wu; S. Nguyen; N. Mishra; R. Meyer; M. Kellam; B. Haukness; C. Chevallier; H. Wu; H. Qian; F. Kreupl; G. Bronner

doi:10.1109/IEDM.2014.7047125

Technology and circuit optimization of resistive RAM for low-power, reproducible operation

D. C. Sekar, B. Bateman, U. Raghuram, S. Bowyer, Y. Bai, M. Calarrudo, P. Swab, J. Wu, S. Nguyen, N. Mishra, R. Meyer, M. Kellam, B. Haukness, C. Chevallier, H. Wu, H. Qian, F. Kreupl, G. Bronner

Associate Professorship of Hybrid Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

Low-power, reproducible operation of Resistive RAM (RRAM) requires control of capacitive surge currents during write. We propose a fab-friendly TiN/conductive TaO_x/HfO₂/TiN RRAM with a built-in surge current reduction layer. It reduces worst case write current by 33% and fail bit count by 23× compared to conventional RRAM. A novel circuit to control surge current is demonstrated that improves write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented.

Original language	English
Title of host publication	2014 IEEE International Electron Devices Meeting, IEDM 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	28.3.1-28.3.4
Edition	February
ISBN (Electronic)	9781479980017
DOIs	https://doi.org/10.1109/IEDM.2014.7047125
State	Published - 20 Feb 2015
Event	2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States Duration: 15 Dec 2014 → 17 Dec 2014

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Number	February
Volume	2015-February
ISSN (Print)	0163-1918

Conference

Conference	2014 60th IEEE International Electron Devices Meeting, IEDM 2014
Country/Territory	United States
City	San Francisco
Period	15/12/14 → 17/12/14

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10.1109/IEDM.2014.7047125

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Sekar, D. C., Bateman, B., Raghuram, U., Bowyer, S., Bai, Y., Calarrudo, M., Swab, P., Wu, J., Nguyen, S., Mishra, N., Meyer, R., Kellam, M., Haukness, B., Chevallier, C., Wu, H., Qian, H., Kreupl, F., & Bronner, G. (2015). Technology and circuit optimization of resistive RAM for low-power, reproducible operation. In 2014 IEEE International Electron Devices Meeting, IEDM 2014 (February ed., pp. 28.3.1-28.3.4). Article 7047125 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2014.7047125

Sekar, D. C. ; Bateman, B. ; Raghuram, U. et al. / Technology and circuit optimization of resistive RAM for low-power, reproducible operation. 2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 28.3.1-28.3.4 (Technical Digest - International Electron Devices Meeting, IEDM; February).

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title = "Technology and circuit optimization of resistive RAM for low-power, reproducible operation",

abstract = "Low-power, reproducible operation of Resistive RAM (RRAM) requires control of capacitive surge currents during write. We propose a fab-friendly TiN/conductive TaOx/HfO2/TiN RRAM with a built-in surge current reduction layer. It reduces worst case write current by 33% and fail bit count by 23× compared to conventional RRAM. A novel circuit to control surge current is demonstrated that improves write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented.",

author = "Sekar, {D. C.} and B. Bateman and U. Raghuram and S. Bowyer and Y. Bai and M. Calarrudo and P. Swab and J. Wu and S. Nguyen and N. Mishra and R. Meyer and M. Kellam and B. Haukness and C. Chevallier and H. Wu and H. Qian and F. Kreupl and G. Bronner",

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Sekar, DC, Bateman, B, Raghuram, U, Bowyer, S, Bai, Y, Calarrudo, M, Swab, P, Wu, J, Nguyen, S, Mishra, N, Meyer, R, Kellam, M, Haukness, B, Chevallier, C, Wu, H, Qian, H, Kreupl, F & Bronner, G 2015, Technology and circuit optimization of resistive RAM for low-power, reproducible operation. in 2014 IEEE International Electron Devices Meeting, IEDM 2014. February edn, 7047125, Technical Digest - International Electron Devices Meeting, IEDM, no. February, vol. 2015-February, Institute of Electrical and Electronics Engineers Inc., pp. 28.3.1-28.3.4, 2014 60th IEEE International Electron Devices Meeting, IEDM 2014, San Francisco, United States, 15/12/14. https://doi.org/10.1109/IEDM.2014.7047125

Technology and circuit optimization of resistive RAM for low-power, reproducible operation. / Sekar, D. C.; Bateman, B.; Raghuram, U. et al.
2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 28.3.1-28.3.4 7047125 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Calarrudo, M.

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AU - Wu, J.

AU - Nguyen, S.

AU - Mishra, N.

AU - Meyer, R.

AU - Kellam, M.

AU - Haukness, B.

AU - Chevallier, C.

AU - Wu, H.

AU - Qian, H.

AU - Kreupl, F.

AU - Bronner, G.

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N2 - Low-power, reproducible operation of Resistive RAM (RRAM) requires control of capacitive surge currents during write. We propose a fab-friendly TiN/conductive TaOx/HfO2/TiN RRAM with a built-in surge current reduction layer. It reduces worst case write current by 33% and fail bit count by 23× compared to conventional RRAM. A novel circuit to control surge current is demonstrated that improves write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented.

AB - Low-power, reproducible operation of Resistive RAM (RRAM) requires control of capacitive surge currents during write. We propose a fab-friendly TiN/conductive TaOx/HfO2/TiN RRAM with a built-in surge current reduction layer. It reduces worst case write current by 33% and fail bit count by 23× compared to conventional RRAM. A novel circuit to control surge current is demonstrated that improves write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented.

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PB - Institute of Electrical and Electronics Engineers Inc.

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Sekar DC, Bateman B, Raghuram U, Bowyer S, Bai Y, Calarrudo M et al. Technology and circuit optimization of resistive RAM for low-power, reproducible operation. In 2014 IEEE International Electron Devices Meeting, IEDM 2014. February ed. Institute of Electrical and Electronics Engineers Inc. 2015. p. 28.3.1-28.3.4. 7047125. (Technical Digest - International Electron Devices Meeting, IEDM; February). doi: 10.1109/IEDM.2014.7047125

Technology and circuit optimization of resistive RAM for low-power, reproducible operation

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