Abstract
This paper presents a mixed-signal/multi-language simulation environment for the languages VHDL-AMS, Java, and C++. The environment is implemented in Java and based upon a previously developed VHDL-AMS design environment consisting of a compiler, an elaborator, and a simulator. The latter was extended by open object-oriented Java and C++ interfaces towards system-level simulation capabilities. Obviously, this approach lends itself to a VHDL-centric modeling style. However, it also results in a well-defined overall simulation semantics based on the proven semantic principles of VHDL-AMS. Moreover, the object- oriented Java and C++ interfaces enforce a much better language modeling style than traditional callback-based procedural language interfaces. The presented open architecture provides good capabilities for research in the field of system-level simulation.
| Original language | English |
|---|---|
| Pages (from-to) | 58-62 |
| Number of pages | 5 |
| Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| State | Published - 2000 |
| Externally published | Yes |
| Event | Proceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA Duration: 13 Sep 2000 → 16 Sep 2000 |