Synthesizing multiplier in reversible logic

Sebastian Offermann; Robert Wille; Gerhard W. Dueck; Rolf Drechsler

doi:10.1109/DDECS.2010.5491757

Synthesizing multiplier in reversible logic

Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

In the past, reversible logic has become an intensely studied research topic. This is mainly motivated by its applications in the domain of low-power design and quantum computation. Since reversible logic is subject to certain restrictions (e.g. fanout and feedback are not allowed), traditional synthesis methods are not applicable and specific methods have been developed. In this paper, we focus on synthesis of multiplier circuits in reversible logic. Three methods are presented that address the drawbacks of previous approaches. In particular, the large number of circuit lines in the resulting realizations as well as the poor scalability. Finally, we compare the results to circuits obtained by general purpose synthesis approaches.

Original language	English
Title of host publication	Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
Pages	335-340
Number of pages	6
DOIs	https://doi.org/10.1109/DDECS.2010.5491757
State	Published - 2010
Externally published	Yes
Event	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 - Vienna, Austria Duration: 14 Apr 2010 → 16 Apr 2010

Publication series

Name	Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010

Conference

Conference	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
Country/Territory	Austria
City	Vienna
Period	14/04/10 → 16/04/10

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10.1109/DDECS.2010.5491757

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Offermann, S., Wille, R., Dueck, G. W., & Drechsler, R. (2010). Synthesizing multiplier in reversible logic. In Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 (pp. 335-340). Article 5491757 (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010). https://doi.org/10.1109/DDECS.2010.5491757

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title = "Synthesizing multiplier in reversible logic",

abstract = "In the past, reversible logic has become an intensely studied research topic. This is mainly motivated by its applications in the domain of low-power design and quantum computation. Since reversible logic is subject to certain restrictions (e.g. fanout and feedback are not allowed), traditional synthesis methods are not applicable and specific methods have been developed. In this paper, we focus on synthesis of multiplier circuits in reversible logic. Three methods are presented that address the drawbacks of previous approaches. In particular, the large number of circuit lines in the resulting realizations as well as the poor scalability. Finally, we compare the results to circuits obtained by general purpose synthesis approaches.",

author = "Sebastian Offermann and Robert Wille and Dueck, {Gerhard W.} and Rolf Drechsler",

year = "2010",

doi = "10.1109/DDECS.2010.5491757",

language = "English",

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series = "Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010",

pages = "335--340",

booktitle = "Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010",

note = "13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 ; Conference date: 14-04-2010 Through 16-04-2010",

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Offermann, S, Wille, R, Dueck, GW & Drechsler, R 2010, Synthesizing multiplier in reversible logic. in Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010., 5491757, Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, pp. 335-340, 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, 14/04/10. https://doi.org/10.1109/DDECS.2010.5491757

Synthesizing multiplier in reversible logic. / Offermann, Sebastian; Wille, Robert; Dueck, Gerhard W. et al.
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. 2010. p. 335-340 5491757 (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In the past, reversible logic has become an intensely studied research topic. This is mainly motivated by its applications in the domain of low-power design and quantum computation. Since reversible logic is subject to certain restrictions (e.g. fanout and feedback are not allowed), traditional synthesis methods are not applicable and specific methods have been developed. In this paper, we focus on synthesis of multiplier circuits in reversible logic. Three methods are presented that address the drawbacks of previous approaches. In particular, the large number of circuit lines in the resulting realizations as well as the poor scalability. Finally, we compare the results to circuits obtained by general purpose synthesis approaches.

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Offermann S, Wille R, Dueck GW, Drechsler R. Synthesizing multiplier in reversible logic. In Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. 2010. p. 335-340. 5491757. (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010). doi: 10.1109/DDECS.2010.5491757

Synthesizing multiplier in reversible logic

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