Abstract
This article presents a new concept for designing on-chip storage and cache that will enable efficient management of intermediate fluid samples during transportation and for reuse. The goal of this synthesis process is to reduce both the overall execution time of the assay and the chip area at the same time. By minimizing channel conflicts and recognizing maximum independent sets, storage requirements are efficiently handled jointly by channels as well as by both distributed and dedicated storage cells.
Original language | English |
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Article number | 2492473 |
Pages (from-to) | 69-75 |
Number of pages | 7 |
Journal | IEEE Design and Test |
Volume | 32 |
Issue number | 6 |
DOIs | |
State | Published - 2015 |