Statistical characterization of hold time violations in 130nm CMOS technology

Keyphrases

• CMOS Technology 100%
• Hold Violation 100%
• Statistical Characterization 100%
• Design Strategy 33%
• Flip-flop 33%
• Logic Path 33%
• Circuit Design 33%
• Register Configuration 33%
• Process Variation 33%
• Synchronous Design 33%
• Measurement Resolution 33%
• Statistical Variation 33%
• Low Power CMOS 33%
• Race Condition 33%
• Clock Edge 33%
• Statistical Process 33%
• Data Skew 33%
• Programmable Clocks 33%
• On-chip Measurement 33%
• Die-to-die 33%

Engineering

• Hold Time 100%
• Statistical Characterization 100%
• Flip Flop Circuits 33%
• Circuit Design 33%
• Statistical Variation 33%
• Hazards and Race Conditions 33%
• Measurement Resolution 33%
• Clock Edge 33%
• Process Variation 33%