Statistical characterization of hold time violations in 130nm CMOS technology

Gustavo Neuberger, Fernanda Kastensmidt, Ricardo Reis, Gilson Wirth, Ralf Brederlow, Christian Pacha

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~∼1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm low-power CMOS technology for various register-to-register configurations and show 3a die-to-die standard deviations of up to 15%.

Original languageEnglish
Title of host publicationESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
Pages114-117
Number of pages4
DOIs
StatePublished - 2006
Externally publishedYes
EventESSCIRC 2006 - 32nd European Solid-State Circuits Conference - Montreux, Switzerland
Duration: 19 Sep 200621 Sep 2006

Publication series

NameESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Conference

ConferenceESSCIRC 2006 - 32nd European Solid-State Circuits Conference
Country/TerritorySwitzerland
CityMontreux
Period19/09/0621/09/06

Fingerprint

Dive into the research topics of 'Statistical characterization of hold time violations in 130nm CMOS technology'. Together they form a unique fingerprint.

Cite this