TY - GEN
T1 - Statistical characterization of hold time violations in 130nm CMOS technology
AU - Neuberger, Gustavo
AU - Kastensmidt, Fernanda
AU - Reis, Ricardo
AU - Wirth, Gilson
AU - Brederlow, Ralf
AU - Pacha, Christian
PY - 2006
Y1 - 2006
N2 - Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~∼1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm low-power CMOS technology for various register-to-register configurations and show 3a die-to-die standard deviations of up to 15%.
AB - Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~∼1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm low-power CMOS technology for various register-to-register configurations and show 3a die-to-die standard deviations of up to 15%.
UR - http://www.scopus.com/inward/record.url?scp=70949087833&partnerID=8YFLogxK
U2 - 10.1109/ESSCIR.2006.307544
DO - 10.1109/ESSCIR.2006.307544
M3 - Conference contribution
AN - SCOPUS:70949087833
SN - 1424403022
SN - 9781424403028
T3 - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
SP - 114
EP - 117
BT - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
T2 - ESSCIRC 2006 - 32nd European Solid-State Circuits Conference
Y2 - 19 September 2006 through 21 September 2006
ER -