Speeding up safety verification by fault abstraction and simulation to transaction level

Bogdan Andrei Tabacaru; Moomen Chaari; Wolfgang Ecker; Thomas Kruse; Cristiano Novello

doi:10.1109/VLSI-SoC.2016.7753547

Speeding up safety verification by fault abstraction and simulation to transaction level

Bogdan Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello

Computation, Information and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

The need for safer and more robust hardware systems increased considerably in the automotive industry after the introduction of the safety standard ISO 26262. As a result, fault injection became a major verification milestone for safety-critical applications. However, safety-verification methods for gate level (GL) and RTL models suffer from long simulation time and large fault-injection campaigns due to the high complexity of large-scale SoCs. Virtual prototypes (VP) were employed to address the shortcomings of GL and RTL simulation, however fault injection into VPs usually leads to the observation of different failures than into GL and RTL models. In this paper, we present an approach which ensures 100% correlation of faults injected across VPs and GL models. Using a compiled-code approach, we transform GL net-lists into C++ code, which we then integrate into SystemC/TLM-based VPs. Thus, the new VPs have the same accuracy as the GL net-lists and are executed at near VP speed. Furthermore, since the new models share all fault-injection properties with the original GL net-lists, only realistic failures can be observed after fault injection.

Original language	English
Title of host publication	2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509035618
DOIs	https://doi.org/10.1109/VLSI-SoC.2016.7753547
State	Published - 22 Nov 2016
Event	24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 - Tallinn, Estonia Duration: 26 Sep 2016 → 28 Sep 2016

Publication series

Name	2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

Conference

Conference	24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
Country/Territory	Estonia
City	Tallinn
Period	26/09/16 → 28/09/16

Keywords

Automotive
Fault Injection
ISO 26262
Safety Verification
SystemC
TLM
Virtual Prototyping

Access to Document

10.1109/VLSI-SoC.2016.7753547

Cite this

Tabacaru, B. A., Chaari, M., Ecker, W., Kruse, T., & Novello, C. (2016). Speeding up safety verification by fault abstraction and simulation to transaction level. In 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 Article 7753547 (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-SoC.2016.7753547

Tabacaru, Bogdan Andrei ; Chaari, Moomen ; Ecker, Wolfgang et al. / Speeding up safety verification by fault abstraction and simulation to transaction level. 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016).

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abstract = "The need for safer and more robust hardware systems increased considerably in the automotive industry after the introduction of the safety standard ISO 26262. As a result, fault injection became a major verification milestone for safety-critical applications. However, safety-verification methods for gate level (GL) and RTL models suffer from long simulation time and large fault-injection campaigns due to the high complexity of large-scale SoCs. Virtual prototypes (VP) were employed to address the shortcomings of GL and RTL simulation, however fault injection into VPs usually leads to the observation of different failures than into GL and RTL models. In this paper, we present an approach which ensures 100% correlation of faults injected across VPs and GL models. Using a compiled-code approach, we transform GL net-lists into C++ code, which we then integrate into SystemC/TLM-based VPs. Thus, the new VPs have the same accuracy as the GL net-lists and are executed at near VP speed. Furthermore, since the new models share all fault-injection properties with the original GL net-lists, only realistic failures can be observed after fault injection.",

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Tabacaru, BA, Chaari, M, Ecker, W, Kruse, T & Novello, C 2016, Speeding up safety verification by fault abstraction and simulation to transaction level. in 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016., 7753547, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Institute of Electrical and Electronics Engineers Inc., 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, 26/09/16. https://doi.org/10.1109/VLSI-SoC.2016.7753547

Speeding up safety verification by fault abstraction and simulation to transaction level. / Tabacaru, Bogdan Andrei; Chaari, Moomen; Ecker, Wolfgang et al.
2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7753547 (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Tabacaru, Bogdan Andrei

AU - Chaari, Moomen

AU - Ecker, Wolfgang

AU - Kruse, Thomas

AU - Novello, Cristiano

PY - 2016/11/22

Y1 - 2016/11/22

N2 - The need for safer and more robust hardware systems increased considerably in the automotive industry after the introduction of the safety standard ISO 26262. As a result, fault injection became a major verification milestone for safety-critical applications. However, safety-verification methods for gate level (GL) and RTL models suffer from long simulation time and large fault-injection campaigns due to the high complexity of large-scale SoCs. Virtual prototypes (VP) were employed to address the shortcomings of GL and RTL simulation, however fault injection into VPs usually leads to the observation of different failures than into GL and RTL models. In this paper, we present an approach which ensures 100% correlation of faults injected across VPs and GL models. Using a compiled-code approach, we transform GL net-lists into C++ code, which we then integrate into SystemC/TLM-based VPs. Thus, the new VPs have the same accuracy as the GL net-lists and are executed at near VP speed. Furthermore, since the new models share all fault-injection properties with the original GL net-lists, only realistic failures can be observed after fault injection.

AB - The need for safer and more robust hardware systems increased considerably in the automotive industry after the introduction of the safety standard ISO 26262. As a result, fault injection became a major verification milestone for safety-critical applications. However, safety-verification methods for gate level (GL) and RTL models suffer from long simulation time and large fault-injection campaigns due to the high complexity of large-scale SoCs. Virtual prototypes (VP) were employed to address the shortcomings of GL and RTL simulation, however fault injection into VPs usually leads to the observation of different failures than into GL and RTL models. In this paper, we present an approach which ensures 100% correlation of faults injected across VPs and GL models. Using a compiled-code approach, we transform GL net-lists into C++ code, which we then integrate into SystemC/TLM-based VPs. Thus, the new VPs have the same accuracy as the GL net-lists and are executed at near VP speed. Furthermore, since the new models share all fault-injection properties with the original GL net-lists, only realistic failures can be observed after fault injection.

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KW - ISO 26262

KW - Safety Verification

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M3 - Conference contribution

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BT - 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

Y2 - 26 September 2016 through 28 September 2016

ER -

Tabacaru BA, Chaari M, Ecker W, Kruse T, Novello C. Speeding up safety verification by fault abstraction and simulation to transaction level. In 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7753547. (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016). doi: 10.1109/VLSI-SoC.2016.7753547

Speeding up safety verification by fault abstraction and simulation to transaction level

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