Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V

Endri Kaja, Nicolas Gerlin, Ares Tahiraga, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

As the semiconductor industry rapidly expands, there is a need for new development methods, especially in the domain of safety-critical designs. The ISO 26262 standard plays a crucial role in the automotive industry by requiring systems to operate safely and reduce the chance of critical failures. Advanced, automated approaches are essential to meet these challenges effectively. This paper presents an automated framework for safety verification using the principles of model-driven architecture, which aims to increase the efficiency, quality, and trustworthiness of these systems. It introduces the concept of creating models with different levels of granularity for various components of a design such as gate-level models for the safety-critical parts and Register-Transfer Level (RTL) models for the rest of the designs. The innovation includes adding fault injectors to these models to inject faults directly in the design. Through a holistic generation flow, various safety verification techniques have been explored, including methods based on simulation, emulation, and formal verification. The effectiveness of these methods has been demonstrated in many different industrial desion applications.

Original languageEnglish
Title of host publication37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350366884
DOIs
StatePublished - 2024
Event37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024 - Didcot, United Kingdom
Duration: 8 Oct 202410 Oct 2024

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
ISSN (Print)2576-1501
ISSN (Electronic)2765-933X

Conference

Conference37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024
Country/TerritoryUnited Kingdom
CityDidcot
Period8/10/2410/10/24

Keywords

  • Fault Emulation
  • Fault Simulation
  • Formal Verification
  • Model-Driven
  • RISC-V

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