SMART: A simulation tool for analyzing cache access behavior on SMPs

Tianchao Li; Michael Gerndt

doi:10.1109/MASCOTS.2005.66

SMART: A simulation tool for analyzing cache access behavior on SMPs

Tianchao Li, Michael Gerndt

Informatics 10 - Associate Professorship of Architecture of Parallel and Distributed Systems

Technical University of Munich

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

This paper presents SMART - a simulation tool for analyzing the cache access behavior on SMP systems. SMART traps memory access events of multi-threaded applications, simulates the accesses in multiple levels of caches of multiple processors and the shared memory, emulates a novel hardware monitor that records events within given address ranges of interest, and presents the result as event counts or histogram in arbitrary granularity. Used independently or together with the advanced tools developed in the EP-Cache project, SMART can help evaluate the performance of multi-threaded applications with different hardware configurations and facilitate the application of effective code transformations for optimization.

Original language	English
Article number	1521178
Pages (from-to)	525-528
Number of pages	4
Journal	Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS
Volume	2005
DOIs	https://doi.org/10.1109/MASCOTS.2005.66
State	Published - 2005
Event	MASCOTS 2005: 13th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems - Atlanta, GA, United States Duration: 27 Sep 2005 → 29 Sep 2005

Access to Document

10.1109/MASCOTS.2005.66

Cite this

@article{8908e9f825624d0f987155ee71fd1b79,

title = "SMART: A simulation tool for analyzing cache access behavior on SMPs",

abstract = "This paper presents SMART - a simulation tool for analyzing the cache access behavior on SMP systems. SMART traps memory access events of multi-threaded applications, simulates the accesses in multiple levels of caches of multiple processors and the shared memory, emulates a novel hardware monitor that records events within given address ranges of interest, and presents the result as event counts or histogram in arbitrary granularity. Used independently or together with the advanced tools developed in the EP-Cache project, SMART can help evaluate the performance of multi-threaded applications with different hardware configurations and facilitate the application of effective code transformations for optimization.",

author = "Tianchao Li and Michael Gerndt",

year = "2005",

doi = "10.1109/MASCOTS.2005.66",

language = "English",

volume = "2005",

pages = "525--528",

journal = "Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS",

issn = "1526-7539",

publisher = "IEEE Computer Society",

note = "MASCOTS 2005: 13th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems ; Conference date: 27-09-2005 Through 29-09-2005",

}

SMART: A simulation tool for analyzing cache access behavior on SMPs. / Li, Tianchao; Gerndt, Michael.
In: Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS, Vol. 2005, 1521178, 2005, p. 525-528.

Research output: Contribution to journal › Conference article › peer-review

TY - JOUR

T1 - SMART

T2 - MASCOTS 2005: 13th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems

AU - Li, Tianchao

AU - Gerndt, Michael

PY - 2005

Y1 - 2005

N2 - This paper presents SMART - a simulation tool for analyzing the cache access behavior on SMP systems. SMART traps memory access events of multi-threaded applications, simulates the accesses in multiple levels of caches of multiple processors and the shared memory, emulates a novel hardware monitor that records events within given address ranges of interest, and presents the result as event counts or histogram in arbitrary granularity. Used independently or together with the advanced tools developed in the EP-Cache project, SMART can help evaluate the performance of multi-threaded applications with different hardware configurations and facilitate the application of effective code transformations for optimization.

AB - This paper presents SMART - a simulation tool for analyzing the cache access behavior on SMP systems. SMART traps memory access events of multi-threaded applications, simulates the accesses in multiple levels of caches of multiple processors and the shared memory, emulates a novel hardware monitor that records events within given address ranges of interest, and presents the result as event counts or histogram in arbitrary granularity. Used independently or together with the advanced tools developed in the EP-Cache project, SMART can help evaluate the performance of multi-threaded applications with different hardware configurations and facilitate the application of effective code transformations for optimization.

UR - http://www.scopus.com/inward/record.url?scp=33646931218&partnerID=8YFLogxK

U2 - 10.1109/MASCOTS.2005.66

DO - 10.1109/MASCOTS.2005.66

M3 - Conference article

AN - SCOPUS:33646931218

SN - 1526-7539

VL - 2005

SP - 525

EP - 528

JO - Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS

JF - Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS

M1 - 1521178

Y2 - 27 September 2005 through 29 September 2005

ER -

SMART: A simulation tool for analyzing cache access behavior on SMPs

Abstract

Access to Document

Other files and links

Fingerprint

Cite this