Single-source hardware modeling of different abstraction levels with state charts

Rainer Findenig; Thomas Leitner; Wolfgang Ecker

doi:10.1109/HLDVT.2012.6418241

Single-source hardware modeling of different abstraction levels with state charts

Rainer Findenig, Thomas Leitner, Wolfgang Ecker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents an approach and a framework for hardware modeling on different abstraction levels, from untimed to cycle-accurate. Being based on UML State Charts, the graphical input language is intuitive to use and can directly serve as the documentation of the model. Compared to previous approaches, we propose an extension to UML that allows specifying all supported abstraction levels of a model in a single source, easing both development and debugging. We also present a code generator that allows selecting a specific abstraction level from the model to automatically generate SystemC code for it. Additionally, we use a modeling style extending existing work for purely cycle-accurate State Charts so that a previously presented code generation approach for VHDL can be reused.

Original language	English
Title of host publication	2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012
Pages	41-48
Number of pages	8
DOIs	https://doi.org/10.1109/HLDVT.2012.6418241
State	Published - 2012
Externally published	Yes
Event	2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012 - Huntington Beach, CA, United States Duration: 9 Nov 2012 → 10 Nov 2012

Publication series

Name	Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
ISSN (Print)	1552-6674

Conference

Conference	2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012
Country/Territory	United States
City	Huntington Beach, CA
Period	9/11/12 → 10/11/12

Access to Document

10.1109/HLDVT.2012.6418241

Cite this

Findenig, R., Leitner, T., & Ecker, W. (2012). Single-source hardware modeling of different abstraction levels with state charts. In 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012 (pp. 41-48). Article 6418241 (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT). https://doi.org/10.1109/HLDVT.2012.6418241

@inproceedings{8996a7cc2d374062abd8089265fb6ee4,

title = "Single-source hardware modeling of different abstraction levels with state charts",

abstract = "This paper presents an approach and a framework for hardware modeling on different abstraction levels, from untimed to cycle-accurate. Being based on UML State Charts, the graphical input language is intuitive to use and can directly serve as the documentation of the model. Compared to previous approaches, we propose an extension to UML that allows specifying all supported abstraction levels of a model in a single source, easing both development and debugging. We also present a code generator that allows selecting a specific abstraction level from the model to automatically generate SystemC code for it. Additionally, we use a modeling style extending existing work for purely cycle-accurate State Charts so that a previously presented code generation approach for VHDL can be reused.",

author = "Rainer Findenig and Thomas Leitner and Wolfgang Ecker",

year = "2012",

doi = "10.1109/HLDVT.2012.6418241",

language = "English",

isbn = "9781467328975",

series = "Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT",

pages = "41--48",

booktitle = "2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012",

note = "2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012 ; Conference date: 09-11-2012 Through 10-11-2012",

}

Findenig, R, Leitner, T & Ecker, W 2012, Single-source hardware modeling of different abstraction levels with state charts. in 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012., 6418241, Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT, pp. 41-48, 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012, Huntington Beach, CA, United States, 9/11/12. https://doi.org/10.1109/HLDVT.2012.6418241

Single-source hardware modeling of different abstraction levels with state charts. / Findenig, Rainer; Leitner, Thomas; Ecker, Wolfgang.
2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012. 2012. p. 41-48 6418241 (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Single-source hardware modeling of different abstraction levels with state charts

AU - Findenig, Rainer

AU - Leitner, Thomas

AU - Ecker, Wolfgang

PY - 2012

Y1 - 2012

N2 - This paper presents an approach and a framework for hardware modeling on different abstraction levels, from untimed to cycle-accurate. Being based on UML State Charts, the graphical input language is intuitive to use and can directly serve as the documentation of the model. Compared to previous approaches, we propose an extension to UML that allows specifying all supported abstraction levels of a model in a single source, easing both development and debugging. We also present a code generator that allows selecting a specific abstraction level from the model to automatically generate SystemC code for it. Additionally, we use a modeling style extending existing work for purely cycle-accurate State Charts so that a previously presented code generation approach for VHDL can be reused.

AB - This paper presents an approach and a framework for hardware modeling on different abstraction levels, from untimed to cycle-accurate. Being based on UML State Charts, the graphical input language is intuitive to use and can directly serve as the documentation of the model. Compared to previous approaches, we propose an extension to UML that allows specifying all supported abstraction levels of a model in a single source, easing both development and debugging. We also present a code generator that allows selecting a specific abstraction level from the model to automatically generate SystemC code for it. Additionally, we use a modeling style extending existing work for purely cycle-accurate State Charts so that a previously presented code generation approach for VHDL can be reused.

UR - http://www.scopus.com/inward/record.url?scp=84874315967&partnerID=8YFLogxK

U2 - 10.1109/HLDVT.2012.6418241

DO - 10.1109/HLDVT.2012.6418241

M3 - Conference contribution

AN - SCOPUS:84874315967

SN - 9781467328975

T3 - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

SP - 41

EP - 48

BT - 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012

T2 - 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012

Y2 - 9 November 2012 through 10 November 2012

ER -

Single-source hardware modeling of different abstraction levels with state charts

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