Simulation of the Transient Potential Distribution On-Chip during a Fast ESD Event Based on a Parametric Measurement Analysis

Lena Zeitlhoefler, Friedrich Zur Nieden, Kai Esmark, Gemot Langguth, Martin Sauter, Franz Kreupl

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

ESD events on semiconductor devices in the pico-or nanosecond range cause local potential differences and are often responsible for severe damages of an IC. The presented simulation approach focuses on the simulation of the transient and local potential distribution on the chip during a discharge on wafer-level. In the approach, the total charge is distributed either via the top metal layer and also via the underlying substrate layer dependent on the IC design. The approach consists of a network-based simulation with uniform cells of lumped elements, which values are determined based on measurement data.

Original languageEnglish
Title of host publicationProceedings of the 2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE, EMC EUROPE 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728155791
DOIs
StatePublished - 23 Sep 2020
Event2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE, EMC EUROPE 2020 - Virtual, Rome, Italy
Duration: 23 Sep 202025 Sep 2020

Publication series

NameProceedings of the 2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE, EMC EUROPE 2020

Conference

Conference2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE, EMC EUROPE 2020
Country/TerritoryItaly
CityVirtual, Rome
Period23/09/2025/09/20

Keywords

  • CCTLP
  • CDM
  • ESD
  • device testing

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