Simulation of the Esaki-tunneling FET

Peng Fei Wang, Thomas Nirschl, Doris Schmitt-Landsiedel, Walter Hansch

Research output: Contribution to journalArticlepeer-review

41 Scopus citations

Abstract

As the dimension of the metal oxide semiconductor field effect transistor (MOSFET) keeping scaling, the short channel effects are becoming serious problems. Recently a MOS-based vertical tunneling transistor in silicon was proposed as a possible successor of the MOSFET. In this work, the device simulation of this novel transistor is performed in order to investigate the impacts of doping profile, gate oxide thickness and drain doping level on the device performance. The simulation shows that the sharp doping profile, thin gate oxide thickness and high drain doping level are the key technologies for fabricating the high performance Esaki-tunneling FET. Finally, the optimized device with high performance is proposed.

Original languageEnglish
Pages (from-to)1187-1192
Number of pages6
JournalSolid-State Electronics
Volume47
Issue number7 SPEC.
DOIs
StatePublished - Jul 2003

Keywords

  • Esaki-tunneling FET
  • MOSFET
  • Simulation
  • Zener tunneling

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